Add support for SATA controller on the
DA850/OMAP-L138/AM18x devices.

The patch adds the necessary clocks, platform
resources and a routine to initialize the SATA
controller.

The PHY configuration in this patch is
courtesy the work done by Zegeye Alemu,
Swaminathan and Mansoor Ahamed from TI.

While testing this patch, enable port multiplier
support iff you are actually using one. The
reasons of this behaviour are discussed
here: http://patchwork.ozlabs.org/patch/78163/

ChangeLog:
v3:
Removed fields which were being initialized
to zero in PHY configuration. Moved SATA base
address definition to the top of the file to
make it inline with what is done for the rest
of the modules.
v2:
Addressed comments from Sergei. Removed unnecessary
braces and removed unnecessary else after goto.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This patch allows setting the input clock frequency of the SoC from
the board specific code using the davinci_set_refclk_rate function.
Suggested-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Commit 044ca015 (davinci: da850/omap-l138: add
support for SoC suspend) introduced DA8XX_PLL1_BASE despite PLL1 exists only on
DA850/OMAP-L138 and da850.c even already #define'd DA850_PLL1_BASE. Kill the
duplicate macro, renaming an existing reference to it...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>

Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>

Add spi clock information for da850.
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

The da850 uart pinmux arrays are not used.  Remove them.
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Tested-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

The da850_mmcsd0_pins pinmux array contains pins that are specific to the
da850 evm board (the write protect and card detect GPIO pins).  Move
the array to the board file.
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Tested-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

The da850_mcasp_pins pinmux array is specific to the da850_evm, and is
not generic.  Move the array to the board file, make it static initdata,
and rename it accordingly.
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Tested-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

The da850_emif25_pins pinmux array is not used.  Remove it.
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Tested-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

The da850_cpgmac_pins pinmux array is not used.  Remove it.
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Tested-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

From: Sudhakar Rajashekhara <sudhakar.raj@ti.com>

The JTAG variant code for Rev-2.0 silicon of the OMAP-L138 has changed.
In addition, the variant code for the AM-1808 SoC appears to match
the Rev-2.0 code for the OMAP-L138.  Add an additional entry to support
these chips.

This patch is originally from a patch on the arago project, here:
http://arago-project.org/git/projects/?p=linux-omapl1.git;a=commit;h=6157618435e313a444cdf059702bd34036a6e2b7

Further information related to the need for this patch can be located at
http://e2e.ti.com/support/embedded/f/354/p/67290/248486.aspx
http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-November/021224.html

This patch was tested using an AM-1808 SoC on a MityARM-1808 SoM card.  It
was also tested using a Rev 1.0 silicon OMAP-L138 on a MityDSP-L138F card.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NMichael Williamson <michael.williamson@criticallink.com>
Tested-by: NMichael Williamson <michael.williamson@criticallink.com>
Reported-by: NNicolas Luna <luna.id@gmail.com>
Reviewed-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

This patch adds USB1.1 and USB2.0 clocks for the Hawkboard-L138 system
Signed-off-by: NVictor Rodriguez <vm.rod25@gmail.com>
Tested-by: NRene Gonzalez <renegs.2378@gmail.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

This patch defines Pin Mux configuration to enable MMC/SD
and USB-OHCI on the Hawkboard-L138 system
Signed-off-by: NVictor Rodriguez <vm.rod25@gmail.com>
Tested-by: NRene Gonzalez <renegs.2378@gmail.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

AM18x/DA850/OMAP-L138 SoCs have variants that can operate
at a maximum of 456 MHz at 1.3V operating point. Also the
1.2V operating point has a variant that can support a maximum
of 375 MHz.

This patch adds three new OPPs (456 MHz, 408 MHz and 372 MHz)
to the list of DA850 OPPs.

Not all silicon is qualified to run at higher speeds and
unfortunately the maximum speed the chip can support can only
be determined from the label on the package (not software
readable).

Because of this, we depend on the maximum speed grade information
to be provided to us in some board specific way. The board informs
the maximum speed grade information by setting the da850_max_speed
variable.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Split mmcsd_clk into mmcsd0_clk and mmcsd1_clk and add davinci_mmc.1
in preparation for adding support for MMCSD1 peripheral in DA850.
Signed-off-by: NJuha Kuikka <juha.kuikka@elektrobit.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode
specific pin lists, while what pin group is used is a function of how the board
is wired.  Copy the pin lists to board-da850-evm.c, renaming them accordingly,
and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing
the CPGMAC module as a whole...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Tested-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board
specific and as such shouldn't be in da850.c -- copy them to board-da850-evm.c,
renaming to da850_evm_nand_pins/da850_evm_nor_pins respectively, and merge the
two lists in da850.c into one, representing the EMIF 2.5 module as a whole,
just like we have it in da830.c...

While at it, remove the '__init' modifier from da850_evm_setup_nor_nand() as
this function is called from non '__init' code...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Tested-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF
timing to remain valid even as the PLL0 output is changed by cpufreq
driver to save power.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

For each DA850 OPP, the normal ('NOM') voltage defined in the tecnical
reference manual (TRM) is actually the minimum voltage the frequency
is supported at.

The minimum ('MIN') voltage defined in TRM is meant to take care of
voltage fluctuations and the device should not be run at this voltage
for extended periods of time.

Fix the OPP definitions to define the cvdd_min as the normal voltage
defined in the datasheet.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Current cpufreq code does not consider errors that can occur while
changing voltage. Code to increase CPU  frequency goes ahead even in
the case the regulator has failed to increase the voltage. This leads
to hard error since lower voltages cannot support increased frequency.

Prevent this by not increasing frequency in case increasing voltage
is not successful.

Also, do not lower the voltage if changing the cpu frequency has failed
for some reason.

Note that we do not return error on failure to decrease voltage as
that is not a hard error.

Build fix for non-cpufreq kernels by Caglar Akyuz.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Cc: Caglar Akyuz <caglar@bilkon-kontrol.com.tr>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch helps get rid of the following sparse warnings
of the type:

  CHECK   arch/arm/mach-davinci/da830.c
arch/arm/mach-davinci/da830.c:1026:3: warning: Initializer entry defined twice
arch/arm/mach-davinci/da830.c:1027:3:   also defined here

coming from the irq priorities array init.

Apart from one instance of genuinie repetition, most are are instances
of multiple #defines of the same interrupt number. I have not
removed the multiple definitions from the irq.h file in the hope
that someone might decide to use them as shared interrupts at some
point of time. The priority initialization however needs to be done
only once and hence has been corrected.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch allows for a more flexible ioremap() interception based on iotable
contents.

With this patch, the ioremap() interception code can properly translate
addresses only after davinci_soc_info has been initialized.  Consequently,
in soc-specific init functions, davinci_common_init() has to happen before any
ioremap() attempts. The da8xx init sequence has been suitably modified to meet
this restriction.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the pinmux implementation so as to ioremap() the pinmux
register area on first use.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch implements the following:

 - interrupt initialization uses ioremap() instead of passing a virtual address
   via davinci_soc_info.

 - machine definitions directly point to cp_intc_init() or davinci_irq_init()

 - davinci_intc_type and davinci_intc_base now get initialized in controller
   specific init functions instead of davinci_common_init()

 - minor fix in davinci_irq_init() to use intc_irq_num instead of
   DAVINCI_N_AINTC_IRQ
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the psc and clock control code to use ioremap()ed
registers.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch eliminates IO_ADDRESS() usage for Davinci timer definitions.  The
timer code has correspondingly been modified to ioremap() MMRs instead.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch replaces the jtag id base info in davinci_soc_info with a physical
address which is then ioremap()ed within common code.

This patch (in combination with a similar change for PSC) will allow us to
eliminate the SYSCFG nastiness in DA8xx code.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the gpio_base definition in davinci_soc_info to be a
physical address, which is then ioremap()ed by the gpio initialization
function.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The earlier watchdog reset mechanism had a couple of limitations.  First, it
embedded a reference to "davinci_wdt_device" inside common code.  This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.

With this patch, davinci_watchdog_reset() now takes the platform device as an
argument.  The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device.  arch_reset() then uses these
elements to reset the system in a SoC specific fashion.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch allows for gpio controllers that deviate from those found on
traditional davinci socs.  davinci_soc_info has an added field to indicate the
soc-specific gpio controller type.  The gpio initialization code then bails
out if necessary.

More elements (tnetv107x) to be added later into enum davinci_gpio_type.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup'
and use clkdev_add_table() to add the list of clocks in one go.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds support for registering for suspend-to-RAM
functionality on da850/omap-l138 SoCs.

da850 supports wakeup based on external event and RTC
alarm.

Currently only RTC alarm based wakeup is supported.
Support for wakeup based on external event will be
added as later improvements.

For scheduling an alarm event on RTC some useful code
is present in Documentation/rtc.txt
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Create static map for internal SRAM and populate SRAM base
and size in soc_info structure to allow SRAM allocation
functions from arch/arm/mach-davinci/sram.c to work.

On DA850 SRAM is used for suspend-to-RAM implementation
in places where DDR2 cannot be accessed as its clocks are
stopped.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

On omap-l1 devices the PLL registers can be locked from
writes. Currently the cpufreq rate setting code unlocks
PLL0 before the write actually happens. With suspend
support getting added PLL1 registers need be be unlocked
as well.

To facilitate this, unlock both PLLs during the init time
itself.

This also obviates the need to unlock PLL registers for
each CPUFreq transtition.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

OMAP-L138 adds a second SYSCFG region having useful functionality
like deep sleep, pull up/down control and SATA clock stop.

This patch makes provision for accessing registers from second
SYSCFG region in da8xx code.

Note that OMAP-L137 has a single SYSCFG region.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Using a device_initcall() for initializing the voltage regulator
on DA850 is not such a good idea because it gets called for all
platforms - even those who do not have a regulator implemented.
This leads to a big fat warning message during boot-up when
regulator cannot be found.

Instead, tie initialization of voltage regulator to cpufreq init.
Define a platform specific init call which in case of DA850 gets
used for initializing the regulator. On other future platforms it
can be used for other purposes.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

In the McASP clock definition add a flag to indicate that the peripheral clock
belongs to ASYNC3 clock domain.
Signed-off-by: NChaithrika U S <chaithrika@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

There have accumulated quite a lot of them after the code reorganizations...

In several cases I had to replace #include <linux/dma-mapping.h> which wasn't
needed directly but happened to #include <linux/err.h> which was needed.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

DA850/OMAP-L138 EVM has a RMII Ethernet PHY on the UI daughter card. The PHY
is enabled by proper programming of the IO Expander (TCA6416) ports. Also for
RMII PHY to work, the MDIO clock of MII PHY has to be disabled since both the
PHYs have the same address. This is done via the GPIO2[6] pin. This patch adds
support for RMII PHY.

This patch also adds a menuconfig option to select one or no peripheral
connected to expander. Currently, sub-options in this menu are RMII and no
peripheral.This menuconfig option is similar to the one present for UI card on
DA830/OMAP-L137 EVM.
Signed-off-by: NChaithrika U S <chaithrika@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Replace badly chosen 'psc_ctlr' name of the 'struct clk' field (PSC already
means "Power and Sleep Controller", so the '_ctlr' postfix makes the name
tautological) with technically correct 'gpsc' (Global PSC -- which contains
all the module registers).
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>