1. 04 4月, 2014 5 次提交
  2. 23 3月, 2014 1 次提交
  3. 08 3月, 2014 3 次提交
    • M
      ARM: 7992/1: boot: compressed: ignore bswapsdi2.S · 38e0b088
      Mark Rutland 提交于
      Commit 017f161a (ARM: 7877/1: use built-in byte swap function) added
      bswapsdi2.{o,S} to arch/arm/boot/compressed/Makefile, but didn't update
      the .gitignore. Thus after a a build git status shows bswapsdi2.S as a
      new file, which is a little annoying.
      
      This patch updates arch/arm/boot/compressed/.gitignore to ignore
      bswapsdi2.S, as we already do for ashldi3.S and others.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NNicolas Pitre <nico@linaro.org>
      Acked-by: NKim Phillips <kim.phillips@freescale.com>
      Cc: David Woodhouse <David.Woodhouse@intel.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      38e0b088
    • L
      ARM: 7991/1: sa1100: fix compile problem on Collie · 052450fd
      Linus Walleij 提交于
      Due to a problem in the MFD Kconfig it was not possible to
      compile the UCB battery driver for the Collie SA1100 system,
      in turn making it impossible to compile in the battery driver.
      (See patch "mfd: include all drivers in subsystem menu".)
      
      After fixing the MFD Kconfig (separate patch) a compile error
      appears in the Collie battery driver due to the <mach/collie.h>
      implicitly requiring <mach/hardware.h> through <linux/gpio.h>
      via <mach/gpio.h> prior to commit
      40ca061b "ARM: 7841/1: sa1100: remove complex GPIO interface".
      
      Fix this up by including the required header into
      <mach/collie.h>.
      
      Cc: stable@vger.kernel.org
      Cc: Andrea Adami <andrea.adami@gmail.com>
      Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      052450fd
    • R
      ARM: fix noMMU kallsyms symbol filtering · 006fa259
      Russell King 提交于
      With noMMU, CONFIG_PAGE_OFFSET was not being set correctly.  As there's
      no MMU, PAGE_OFFSET should be equal to PHYS_OFFSET in all cases.  This
      commit makes that explicit.
      
      Since we do this, we don't need to mess around in asm/memory.h with
      ifdefs to sort this out, so let's get rid of that, and there's no point
      offering the "Memory split" option for noMMU as that's meaningless
      there.
      
      Fixes: b9b32bf7 ("ARM: use linker magic for vectors and vector stubs")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      006fa259
  4. 03 3月, 2014 2 次提交
    • U
      ARM: XEN depends on having a MMU · 7693decc
      Uwe Kleine-König 提交于
      arch/arm/xen/enlighten.c (and maybe others) use MMU-specific functions
      like pte_mkspecial which are only available on MMU builds. So let XEN
      depend on MMU.
      Suggested-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
      Acked-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
      Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      7693decc
    • M
      ARM: dts: omap3-gta04: Add ti,omap36xx to compatible property to avoid problems with booting · ae41a303
      Marek Belisko 提交于
      Without that change booting leads to crash with more warnings like below:
      [    0.284454] omap_hwmod: uart4: cannot clk_get main_clk uart4_fck
      [    0.284484] omap_hwmod: uart4: cannot _init_clocks
      [    0.284484] ------------[ cut here ]------------
      [    0.284545] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2543 _init+0x300/0x3e4()
      [    0.284545] omap_hwmod: uart4: couldn't init clocks
      [    0.284576] Modules linked in:
      [    0.284606] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-next-20140124-00020-gd2aefec-dirty #26
      [    0.284637] [<c00151c0>] (unwind_backtrace) from [<c0011e20>] (show_stack+0x10/0x14)
      [    0.284667] [<c0011e20>] (show_stack) from [<c0568544>] (dump_stack+0x7c/0x94)
      [    0.284729] [<c0568544>] (dump_stack) from [<c003ff94>] (warn_slowpath_common+0x6c/0x90)
      [    0.284729] [<c003ff94>] (warn_slowpath_common) from [<c003ffe8>] (warn_slowpath_fmt+0x30/0x40)
      [    0.284759] [<c003ffe8>] (warn_slowpath_fmt) from [<c07d1be8>] (_init+0x300/0x3e4)
      [    0.284790] [<c07d1be8>] (_init) from [<c07d217c>] (__omap_hwmod_setup_all+0x40/0x8c)
      [    0.284820] [<c07d217c>] (__omap_hwmod_setup_all) from [<c0008918>] (do_one_initcall+0xe8/0x14c)
      [    0.284851] [<c0008918>] (do_one_initcall) from [<c07c5c18>] (kernel_init_freeable+0x104/0x1c8)
      [    0.284881] [<c07c5c18>] (kernel_init_freeable) from [<c0563524>] (kernel_init+0x8/0x118)
      [    0.284912] [<c0563524>] (kernel_init) from [<c000e368>] (ret_from_fork+0x14/0x2c)
      [    0.285064] ---[ end trace 63de210ad43b627d ]---
      
      Reference:
      https://lkml.org/lkml/2013/10/8/553Signed-off-by: NMarek Belisko <marek@goldelico.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      ae41a303
  5. 01 3月, 2014 2 次提交
  6. 28 2月, 2014 2 次提交
    • T
      ARM: OMAP3: Fix pinctrl interrupts for core2 · 4b416368
      Tony Lindgren 提交于
      After splitting padconf core into two parts to avoid exposing
      unaccessable registers, the new padconf core2 domain was left
      without a wake-up interrupt.
      
      Fix the issue by passing the shared wake-up interrupt in
      platform data like we do for padconf core and wkup domains
      already.
      
      Fixes: 3d495383 (ARM: dts: Split omap3 pinmux core device)
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      4b416368
    • M
      arm/arm64: KVM: detect CPU reset on CPU_PM_EXIT · b20c9f29
      Marc Zyngier 提交于
      Commit 1fcf7ce0 (arm: kvm: implement CPU PM notifier) added
      support for CPU power-management, using a cpu_notifier to re-init
      KVM on a CPU that entered CPU idle.
      
      The code assumed that a CPU entering idle would actually be powered
      off, loosing its state entierely, and would then need to be
      reinitialized. It turns out that this is not always the case, and
      some HW performs CPU PM without actually killing the core. In this
      case, we try to reinitialize KVM while it is still live. It ends up
      badly, as reported by Andre Przywara (using a Calxeda Midway):
      
      [    3.663897] Kernel panic - not syncing: unexpected prefetch abort in Hyp mode at: 0x685760
      [    3.663897] unexpected data abort in Hyp mode at: 0xc067d150
      [    3.663897] unexpected HVC/SVC trap in Hyp mode at: 0xc0901dd0
      
      The trick here is to detect if we've been through a full re-init or
      not by looking at HVBAR (VBAR_EL2 on arm64). This involves
      implementing the backend for __hyp_get_vectors in the main KVM HYP
      code (rather small), and checking the return value against the
      default one when the CPU notifier is called on CPU_PM_EXIT.
      Reported-by: NAndre Przywara <osp@andrep.de>
      Tested-by: NAndre Przywara <osp@andrep.de>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Rob Herring <rob.herring@linaro.org>
      Acked-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      b20c9f29
  7. 25 2月, 2014 1 次提交
  8. 22 2月, 2014 2 次提交
  9. 21 2月, 2014 1 次提交
    • T
      ARM: 7980/1: kernel: improve error message when LPAE config doesn't match CPU · b3634575
      Thomas Petazzoni 提交于
      Currently, when the kernel is configured with LPAE support, but the
      CPU doesn't support it, the error message is fairly cryptic:
      
        Error: unrecognized/unsupported processor variant (0x561f5811).
      
      This messages is normally shown when there is an issue when comparing
      the processor ID (CP15 0, c0, c0) with the values/masks described in
      proc-v7.S. However, the same message is displayed when LPAE support is
      enabled in the kernel configuration, but not available in the CPU,
      after looking at ID_MMFR0 (CP15 0, c0, c1, 4). Having the same error
      message is highly misleading.
      
      This commit improves this by showing a different error message when
      this situation occurs:
      
        Error: Kernel with LPAE support, but CPU does not support LPAE.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      b3634575
  10. 20 2月, 2014 5 次提交
  11. 19 2月, 2014 6 次提交
  12. 18 2月, 2014 1 次提交
  13. 15 2月, 2014 1 次提交
  14. 14 2月, 2014 8 次提交