In particular, avoid membar instructions in the delay
slot of a jmpl instruction.

UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51

The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.

If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.

We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

warning: untested, but it there's not too much chance for screwups
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This case actually can get exercised a lot during an ELF
coredump of a process which contains a lot of non-COW'd
anonymous pages.  GDB has this test case which in partiaular
creates near terabyte process full of ZERO_PAGEes.  It takes
forever to just walk through the page tables because of
all of these spurious cache flushes on sparc64.

With this change it takes only a second or so.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!