- 12 10月, 2011 1 次提交
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由 Ilija Hadzic 提交于
Looks like the same pcie gen2 speed initialization for Evergreen also works on Cayman and seems to come up fine, so enable it if the module parameter says so Signed-off-by: NIlija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 06 9月, 2011 1 次提交
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由 Tormod Volden 提交于
This was previously done for r300 only. Use %016llX instead of %08X for printing the table address. Also fix typos in gart warning messages. Signed-off-by: NTormod Volden <debian.tormod@gmail.com> Reviewed-by: NMichel Dänzer <michel@daenzer.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 02 9月, 2011 1 次提交
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由 Alex Deucher 提交于
If the bios or OS sets the pci max read request size to 0 or an invalid value (6,7), it can result in a hang or slowdown. Check and set it to something sane if it's invalid. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=42162 v2: use pci reg defines from include/linux/pci_regs.h Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 30 8月, 2011 1 次提交
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由 Jerome Glisse 提交于
For some reason SPI block is in broken state after module unloading. This lead to broken rendering after reloading module. Fix this by reseting SPI block in CP resume function Signed-off-by: Jerome Glisse <jglisse@redhat.com Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 7月, 2011 1 次提交
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由 Alex Deucher 提交于
The 3D driver need to get the pipe to backend map to certain things. Add a query to get the info. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 07 7月, 2011 1 次提交
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由 Jerome Glisse 提交于
ib pool weren't free for various newer asic on module unload. This doesn't cause much arm but still could be candidate for stable. Signed-off-by: NJerome Glisse <jglisse@redhat.com> cc: stable@kernel.org Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 26 5月, 2011 1 次提交
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由 Alex Deucher 提交于
Allows us to use the 3D engine for memory management and allows us to use vram beyond the BAR aperture. v2: fix copy paste typo Reported-by: NNils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 22 5月, 2011 3 次提交
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由 Dave Airlie 提交于
cayman is reporting the wrong tile config value to userspace, this causes piglit mipmap generation tests to fail. Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
This was leading to a bogus value being programmed to the backend routing register. Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
On cayman we need to set the bit to cause HDP flushes to invalidate the HDP cache also. Reviewed-by: NAlex Deucher <alexdeucher@gmail.com> cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 11 5月, 2011 2 次提交
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由 Alex Deucher 提交于
The TCC disable setup was incorrect. This prevents the GPU from hanging when draw commands are issued. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
We are accessing totally the wrong struct in this case, and putting uninitialised values into the GPU, which it doesn't like unsurprisingly. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 03 3月, 2011 7 次提交
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由 Alex Deucher 提交于
These should be handled by the clear_state setup, but set them directly as well just to be sure. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Cayman is different enough from evergreen to warrant it's own functions. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Cayman asics have 3 ring buffers: ring 0 supports both gfx and compute rings 1 and 2 are compute only At the moment we only support ring 0. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
This patch sets up the gart in legacy mode. We probably want to switch to full VM mode at some point. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
This may some work to get accel going. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
The MC ucode is no longer loaded by the vbios tables as on previous asics. It now must be loaded by the driver. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 07 1月, 2011 1 次提交
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由 Alex Deucher 提交于
The MC ucode is no longer loaded by the vbios tables as on previous asics. It now must be loaded by the driver. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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