- 07 12月, 2006 3 次提交
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由 Laurent Vivier 提交于
Find the BBAR register address of each Calgary using the "Extended BIOS Data Area" rather than calculating it ourselves. Also get the bus topology (what PHB each bus is on) from Calgary rather than calculating it ourselves. This patch fixes http://bugzilla.kernel.org/show_bug.cgi?id=7407. Signed-off-by: NLaurent Vivier <Laurent.Vivier@bull.net> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Alan Cox 提交于
Resending as I believe the discussion about them established they were correct. Signed-off-by: NAlan Cox <alan@redhat.com> Signed-off-by: NAndi Kleen <ak@suse.de> Cc: Andi Kleen <ak@suse.de> Signed-off-by: NAndrew Morton <akpm@osdl.org>
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- 22 10月, 2006 2 次提交
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由 Muli Ben-Yehuda 提交于
This patch increases the timeout for PCI split transactions on PHB1 on the first Calgary to work around an issue with the aic94xx adapter. Fixes kernel.org bugzilla #7180 (http://bugzilla.kernel.org/show_bug.cgi?id=7180) Based on excellent debugging and a patch by Darrick J. Wong <djwong@us.ibm.com> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NAndi Kleen <ak@suse.de> Acked-by: NDarrick J. Wong <djwong@us.ibm.com>
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由 Muli Ben-Yehuda 提交于
This patch increases the timeout for PCI split transactions on PHB1 on the first Calgary to work around an issue with the aic94xx adapter. Fixes kernel.org bugzilla #7180 (http://bugzilla.kernel.org/show_bug.cgi?id=7180) Based on excellent debugging and a patch by Darrick J. Wong <djwong@us.ibm.com> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NAndi Kleen <ak@suse.de> Acked-by: NDarrick J. Wong <djwong@us.ibm.com>
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- 06 10月, 2006 4 次提交
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由 Jon Mason 提交于
Make the references to the bus number in hex instead of decimal, as that is the way that lspci prints out the bus numbers. Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Jon Mason 提交于
Also add copyright for work done after leaving IBM. Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Jon Mason 提交于
The purpose of the code being modified is to determine the location of the calgary chip address space. This is done by a magical formula of FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase) to find the offset where BIOS puts it. In this formula, OneBasedChassisNumber corresponds to the NUMA node, and rionodeid is always 2 or 3 depending on which chip in the system it is. The problem was that we had an off by one error that caused us to account some busses to the wrong chip and thus give them the wrong address space. Fixes RH bugzilla #203971. Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-bu: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Jon Mason 提交于
calgary_init's for loop does not correspond to the actual device being checked, which makes its upperbound check for array overflow useless. Changing this to a do-while loop is the correct way of doing this. There should be no possibility of spinning forever in this loop, as pci_get_device states that it will go through all iterations, then return NULL (thus breaking the loop). Signed-off-by: NJon Mason <jdmason@kudzu.us> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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- 04 10月, 2006 1 次提交
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由 Dave Jones 提交于
kbuild explicitly includes this at build time. Signed-off-by: NDave Jones <davej@redhat.com>
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- 26 9月, 2006 11 次提交
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由 Andi Kleen 提交于
Some buggy systems can machine check when config space accesses happen for some non existent devices. i386/x86-64 do some early device scans that might trigger this. Allow pci=noearly to disable this. Also when type 1 is disabling also don't do any early accesses which are always type1. This moves the pci= configuration parsing to be a early parameter. I don't think this can break anything because it only changes a single global that is only used by PCI. Cc: gregkh@suse.de Cc: Trammell Hudson <hudson@osresearch.net> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
tce_cache_blast_stress was useful during bringup to stress the IOMMU's cache flushing. Now that we quiesce DMAs on every cache flush, using _stress() brings the machine down to its knees once you put it under load. Remove this debug / bringup code that isn't useful anymore completely. Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Introduce new function verify_bit_range(). Define two versions, one for CONFIG_IOMMU_DEBUG enabled and one for disabled. Previously we were checking that the bitmap was consistent every time we allocated or freed an entry in the TCE table, which is good for debugging but incurs an unnecessary penalty on non debug builds. Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Make translation_disabled a uchar rather than an int Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
The pci_get_device() API decrements the reference count on the 'from' parameter when it continues searching. Therefore, take a ref count on Calgary bus when we initialize them in either translated or non-translated mode. Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
We were freeing the iommu_table and leaking the bitmap pages. Also rename it to calgary_free_bus, which is more accurate. Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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由 Muli Ben-Yehuda 提交于
Move the tce_table_kva array, disabled bitmap and bus_to_phb array into a new per bus 'struct calgary_bus_info'. Also slightly reorganize build_tce_table and tce_table_setparms to avoid exporting bus_info to tce.c. Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de>
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- 30 7月, 2006 2 次提交
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由 Jon Mason 提交于
Calgary hits a NULL pointer dereference when booting in a multi-chassis NUMA system. See Redhat bugzilla number 198498, found by Konrad Rzeszutek (konradr@redhat.com). There are many issues that had to be resolved to fix this problem. Firstly when I originally wrote the code to handle NUMA systems, I had a large misunderstanding that was not corrected until now. That was that I thought the "number of nodes online" referred to number of physical systems connected. So that if NUMA was disabled, there would only be 1 node and it would only show that node's PCI bus. In reality if NUMA is disabled, the system displays all of the connected chassis as one node but is only ignorant of the delays in accessing main memory. Therefore, references to num_online_nodes() and MAX_NUMNODES are incorrect and need to be set to the maximum number of nodes that can be accessed (which are 8). I created a variable, MAX_NUM_CHASSIS, and set it to 8 to fix this. Secondly, when walking the PCI in detect_calgary, the code only checked the first "slot" when looking to see if a device is present. This will work for most cases, but unfortunately it isn't always the case. In the NUMA MXE drawers, there are USB devices present on the 3rd slot (with slot 1 being empty). So, to work around this, all slots (up to 8) are scanned to see if there are any devices present. Lastly, the bus is being enumerated on large systems in a different way the we originally thought. This throws the ugly logic we had out the window. To more elegantly handle this, I reorganized the kva array to be sparse (which removed the need to have any bus number to kva slot logic in tce.c) and created a secondary space array to contain the bus number to phb mapping. With these changes Calgary boots on an x460 with 4 nodes with and without NUMA enabled. Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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由 Muli Ben-Yehuda 提交于
Fixed off-by-one error in detect_calgary and calgary_init which will cause arrays to overflow. Also, removed impossible to hit BUG_ON. Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 11 7月, 2006 1 次提交
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由 Muli Ben-Yehuda 提交于
Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 27 6月, 2006 1 次提交
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由 Jon Mason 提交于
This patch hooks Calgary into the build, the x86-64 IOMMU initialization paths, and introduces the Calgary specific bits. The implementation draws inspiration from both PPC (which has support for the same chip but requires firmware support which we don't have on x86-64) and gart. Calgary is different from gart in that it support a translation table per PHB, as opposed to the single gart aperture. Changes from previous version: * Addition of boot-time disablement for bus-level translation/isolation (e.g, enable userspace DMA for things like X) * Usage of newer IOMMU abstraction functions Signed-off-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NJon Mason <jdmason@us.ibm.com> Signed-off-by: NAndi Kleen <ak@suse.de> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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