Add new clockevent driver that uses the counter present on the MIPS
Global Interrupt Controller.
Signed-off-by: NRaghu Gandham <Raghu.Gandham@imgtec.com>
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Various whitespace and #ifdef removals for GIC and R4K clocksources.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Reorganize some of the GIC clocksource driver code. Below is a list of
the various changes.

  * No longer select CSRC_GIC by default for Malta platform.
  * Limit choice for either the GIC or R4K clocksource, not both.
  * Change location in Makefile.
  * Created new 'gic_read_count' function in common 'irq-gic.c' file.
  * Change 'git_hpt_read' function in 'csrc-gic.c' to use new function.
  * Surround GIC specific code in Malta platform code with #ifdef's.
  * Only initialize the GIC clocksource if it was selected. Original
    code called it unconditionally if a GIC was found.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Move the global variable 'gic_frequency' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Move the global variable 'gic_present' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Add logic needed to handle unaligned accesses in MIPS16e mode.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Add logic needed to properly calculate exceptions for delay slots
when in MIPS16e mode.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Add structures for all the MIPS16e instructions. Also add the
enumerations for all the bit fields for opcodes, functions, etc.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Optimise 'strnlen' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Optimise 'strlen' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Optimise 'strncpy' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Optimise 'memset' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

This adds the option to build the Linux kernel using only the
microMIPS ISA. The resulting kernel binary is, at a minimum,
20% smaller than using the MIPS32R2 ISA.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Partially revert commit e0c14a260d66ba35935600d6435940a566fe806b
and turn off LL/SC when building a pure microMIPS kernel. This is
a temporary fix until the cmpxchg assembly macro functions are
re-written to not use the HI/LO registers in address calculations.

Also add .insn in selected user access functions which would
otherwise produce ISA mode jump incompatibilities. This is also a
temporary fix.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Support vdso in microMIPS mode.
Signed-off-by: NDouglas Leung <Douglas.Leung@imgtec.com>
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Add logic needed to handle unaligned accesses in microMIPS mode.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Add logic needed to properly calculate exceptions for delay slots
when in microMIPS mode.
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Add logic needed to do floating point emulation in microMIPS mode.
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>

The macros did not properly take into account the ISA that
the kernel was being compiled with. A classic MIPS kernel
will have the standard 'uasm_i_##op' macro functions with
'MM_uasm_i_##op' macro functions for the microMIPS version.
A pure microMIPS kernel will have the standard macros with
'CL_uasm_i_##op' macro functions for the classic version.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Jump or branch target addresses have the first bit set. The
original mask did not take this into account and will cause
a field overflow warning for the target address when a jump
immediate instruction is built.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Currently, the following instructions are translated:
- CACHE (indexed)
- CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations,
  but still much faster than a trap.
- mfc0/mtc0: the virtual COP0 registers for the guest are implemented as
  2-D array.
  [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0.
  mfc0/mtc0 operations are transformed to load/stores.
Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Changes for pure microMIPS cores to dynamically determine the ASID
size at boot time.

Includes bug fix https://patchwork.linux-mips.org/patch/5230/Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: NJonas Gorski <jogo@openwrt.org>

Original patch by Ralf Baechle and removed by Harold Koerfgen
with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This
allows for more generic kernels since the size of the ASID
and corresponding masks can be determined at run-time. This
patch is also required for the new Aptiv cores and has been
tested on Malta and Malta Aptiv platforms.

[ralf@linux-mips.org: Added relevant part of fix
https://patchwork.linux-mips.org/patch/5213/]
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Clean-up code according to the 'checkpatch.pl' script.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Remove 'arch/mips/include/asm/mips-boards/prom.h' and get rid of
all inclusions of it by Malta and SEAD-3 platforms.

[ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS:
ar7 powertv build"].

[ralf@linux-mips.org: Fold in John Crispin <blogic@openwrt.org>'s "MIPS:
unbreak powertv build"].

[ralf@linux-mips.org: Test. Build. Your. Fscking. Code. Or...]
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Remove old YAMON prom code and use common firmware library code.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Remove old YAMON prom code and use common firmware library code.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Add parsing of the environment and command line variables passed to
the kernel to the firmware library.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Add declaration of 'mips_scroll_message' and 'mips_display_message'
to the common generic header file for the MIPS Technologies Inc.
development boards.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Setting the LED_CORE_SUSPENDRESUME flag causes the LED driver core to call
led_classdev_suspend/led_classdev_resume during suspend/resume. Since this is
exactly what the driver's custom suspend/resume callbacks do we can replace them
by setting the LED_CORE_SUSPENDRESUME flag.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Note that this file is statically linked with the rest of the host kernel (KSEG0). This is because kernel modules are
loaded into mapped space on MIPS and we want to make sure that we don't get any host kernel TLB faults while
manipulating TLBs.
- Virtual Guest TLBs are implemented as 64 entry array regardless of the number of host TLB entries.
- Shadow TLBs map Guest virtual addresses to Host physical addresses.

    - TLB miss handling details:
        Guest KSEG0 TLBMISS (0x40000000 – 0x60000000): Transparent to the Guest.
        Guest KSEG2/3 (0x60000000 – 0x80000000) & Guest UM TLBMISS (0x00000000 – 0x40000000)
            Lookup in Guest/Virtual TLB
            If an entry doesn’t match
                deliver appropriate TLBMISS LD/ST exception to the guest
            If entry does exist in the Guest TLB and is NOT Valid
                Deliver TLB invalid exception to the guest
            If entry does exist in the Guest TLB and is VALID
                Inject the TLB entry into the Shadow TLB
Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>