1. 10 8月, 2007 1 次提交
  2. 21 7月, 2007 9 次提交
  3. 18 7月, 2007 1 次提交
  4. 03 7月, 2007 2 次提交
  5. 28 6月, 2007 1 次提交
  6. 09 5月, 2007 1 次提交
    • B
      [POWERPC] Introduce address space "slices" · d0f13e3c
      Benjamin Herrenschmidt 提交于
      The basic issue is to be able to do what hugetlbfs does but with
      different page sizes for some other special filesystems; more
      specifically, my need is:
      
       - Huge pages
      
       - SPE local store mappings using 64K pages on a 4K base page size
      kernel on Cell
      
       - Some special 4K segments in 64K-page kernels for mapping a dodgy
      type of powerpc-specific infiniband hardware that requires 4K MMU
      mappings for various reasons I won't explain here.
      
      The main issues are:
      
       - To maintain/keep track of the page size per "segment" (as we can
      only have one page size per segment on powerpc, which are 256MB
      divisions of the address space).
      
       - To make sure special mappings stay within their allotted
      "segments" (including MAP_FIXED crap)
      
       - To make sure everybody else doesn't mmap/brk/grow_stack into a
      "segment" that is used for a special mapping
      
      Some of the necessary mechanisms to handle that were present in the
      hugetlbfs code, but mostly in ways not suitable for anything else.
      
      The patch relies on some changes to the generic get_unmapped_area()
      that just got merged.  It still hijacks hugetlb callbacks here or
      there as the generic code hasn't been entirely cleaned up yet but
      that shouldn't be a problem.
      
      So what is a slice ?  Well, I re-used the mechanism used formerly by our
      hugetlbfs implementation which divides the address space in
      "meta-segments" which I called "slices".  The division is done using
      256MB slices below 4G, and 1T slices above.  Thus the address space is
      divided currently into 16 "low" slices and 16 "high" slices.  (Special
      case: high slice 0 is the area between 4G and 1T).
      
      Doing so simplifies significantly the tracking of segments and avoids
      having to keep track of all the 256MB segments in the address space.
      
      While I used the "concepts" of hugetlbfs, I mostly re-implemented
      everything in a more generic way and "ported" hugetlbfs to it.
      
      Slices can have an associated page size, which is encoded in the mmu
      context and used by the SLB miss handler to set the segment sizes.  The
      hash code currently doesn't care, it has a specific check for hugepages,
      though I might add a mechanism to provide per-slice hash mapping
      functions in the future.
      
      The slice code provide a pair of "generic" get_unmapped_area() (bottomup
      and topdown) functions that should work with any slice size.  There is
      some trickiness here so I would appreciate people to have a look at the
      implementation of these and let me know if I got something wrong.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d0f13e3c
  7. 30 4月, 2007 1 次提交
  8. 24 4月, 2007 4 次提交
  9. 10 3月, 2007 1 次提交
    • B
      [POWERPC] Fix spu SLB invalidations · 94b2a439
      Benjamin Herrenschmidt 提交于
      The SPU code doesn't properly invalidate SPUs SLBs when necessary,
      for example when changing a segment size from the hugetlbfs code. In
      addition, it saves and restores the SLB content on context switches
      which makes it harder to properly handle those invalidations.
      
      This patch removes the saving & restoring for now, something more
      efficient might be found later on. It also adds a spu_flush_all_slbs(mm)
      that can be used by the core mm code to flush the SLBs of all SPEs that
      are running a given mm at the time of the flush.
      
      In order to do that, it adds a spinlock to the list of all SPEs and move
      some bits & pieces from spufs to spu_base.c
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      94b2a439
  10. 24 1月, 2007 1 次提交
  11. 04 12月, 2006 4 次提交
  12. 10 11月, 2006 1 次提交
  13. 25 10月, 2006 5 次提交
  14. 16 10月, 2006 1 次提交
  15. 07 10月, 2006 1 次提交
  16. 05 10月, 2006 4 次提交
    • A
      [POWERPC] spufs: support new OF device tree format · 7650f2f2
      Arnd Bergmann 提交于
      The properties we used traditionally in the device tree are somewhat
      nonstandard.  This adds support for a more conventional format using
      'interrupts' and 'reg' properties.
      
      The interrupts are specified in three cells (class 0, 1 and 2) and
      registered at the interrupt-parent.
      
      The reg property contains either three or four register areas in the
      order 'local-store', 'problem', 'priv2', and 'priv1', so the priv1 one
      can be left out in case of hypervisor driven systems that access these
      through hcalls.
      Signed-off-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      7650f2f2
    • A
      [POWERPC] spufs: remove support for ancient firmware · 772920e5
      Arnd Bergmann 提交于
      Any firmware that still uses the 'spc' nodes already
      stopped running for other reasons, so let's get rid of this.
      Signed-off-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      772920e5
    • A
      [POWERPC] spufs: implement error event delivery to user space · 9add11da
      Arnd Bergmann 提交于
      This tries to fix spufs so we have an interface closer to what is
      specified in the man page for events returned in the third argument of
      spu_run.
      
      Fortunately, libspe has never been using the returned contents of that
      register, as they were the same as the return code of spu_run (duh!).
      
      Unlike the specification that we never implemented correctly, we now
      require a SPU_CREATE_EVENTS_ENABLED flag passed to spu_create, in
      order to get the new behavior. When this flag is not passed, spu_run
      will simply ignore the third argument now.
      Signed-off-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      9add11da
    • M
      [POWERPC] spufs: scheduler support for NUMA. · a68cf983
      Mark Nutter 提交于
      This patch adds NUMA support to the the spufs scheduler.
      
      The new arch/powerpc/platforms/cell/spufs/sched.c is greatly
      simplified, in an attempt to reduce complexity while adding
      support for NUMA scheduler domains.  SPUs are allocated starting
      from the calling thread's node, moving to others as supported by
      current->cpus_allowed.  Preemption is gone as it was buggy, but
      should be re-enabled in another patch when stable.
      
      The new arch/powerpc/platforms/cell/spu_base.c maintains idle
      lists on a per-node basis, and allows caller to specify which
      node(s) an SPU should be allocated from, while passing -1 tells
      spu_alloc() that any node is allowed.
      
      Since the patch removes the currently implemented preemptive
      scheduling, it is technically a regression, but practically
      all users have since migrated to this version, as it is
      part of the IBM SDK and the yellowdog distribution, so there
      is not much point holding it back while the new preemptive
      scheduling patch gets delayed further.
      Signed-off-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      a68cf983
  17. 04 10月, 2006 1 次提交
    • B
      [POWERPC] Cell interrupt rework · 2e194583
      Benjamin Herrenschmidt 提交于
      This patch reworks the cell iic interrupt handling so that:
      
       - Node ID is back in the interrupt number (only one IRQ host is created
      for all nodes). This allows interrupts from sources on another node to
      be routed non-locally. This will allow possibly one day to fix maxcpus=1
      or 2 and still get interrupts from devices on BE 1. (A bit more fixing
      is needed for that) and it will allow us to implement actual affinity
      control of external interrupts.
      
       - Added handling of the IO exceptions interrupts (badly named, but I
      re-used the name initially used by STI). Those are the interrupts
      exposed by IIC_ISR and IIC_IRR, such as the IOC translation exception,
      performance monitor, etc... Those get their special numbers in the IRQ
      number space and are internally implemented as a cascade on unit 0xe,
      class 1 of each node.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      2e194583
  18. 26 9月, 2006 1 次提交