1. 18 7月, 2014 1 次提交
  2. 20 6月, 2014 1 次提交
    • P
      serial: Fix IGNBRK handling · ef8b9ddc
      Peter Hurley 提交于
      If IGNBRK is set without either BRKINT or PARMRK set, some uart
      drivers send a 0x00 byte for BREAK without the TTYBREAK flag to the
      line discipline, when it should send either nothing or the TTYBREAK flag
      set. This happens because the read_status_mask masks out the BI
      condition, which uart_insert_char() then interprets as a normal 0x00 byte.
      
      SUS v3 is clear regarding the meaning of IGNBRK; Section 11.2.2, General
      Terminal Interface - Input Modes, states:
        "If IGNBRK is set, a break condition detected on input shall be ignored;
         that is, not put on the input queue and therefore not read by any
         process."
      
      Fix read_status_mask to include the BI bit if IGNBRK is set; the
      lsr status retains the BI bit if a BREAK is recv'd, which is
      subsequently ignored in uart_insert_char() when masked with the
      ignore_status_mask.
      
      Affected drivers:
      8250 - all
      serial_txx9
      mfd
      amba-pl010
      amba-pl011
      atmel_serial
      bfin_uart
      dz
      ip22zilog
      max310x
      mxs-auart
      netx-serial
      pnx8xxx_uart
      pxa
      sb1250-duart
      sccnxp
      serial_ks8695
      sirfsoc_uart
      st-asc
      vr41xx_siu
      zs
      sunzilog
      fsl_lpuart
      sunsab
      ucc_uart
      bcm63xx_uart
      sunsu
      efm32-uart
      pmac_zilog
      mpsc
      msm_serial
      m32r_sio
      
      Unaffected drivers:
      omap-serial
      rp2
      sa1100
      imx
      icom
      
      Annotated for fixes:
      altera_uart
      mcf
      
      Drivers without break detection:
      21285
      xilinx-uartps
      altera_jtaguart
      apbuart
      arc-uart
      clps711x
      max3100
      uartlite
      msm_serial_hs
      nwpserial
      lantiq
      vt8500_serial
      
      Unknown:
      samsung
      mpc52xx_uart
      bfin_sport_uart
      cpm_uart/core
      
      Fixes: Bugzilla #71651, '8250_core.c incorrectly handles IGNBRK flag'
      Reported-by: NIvan <athlon_@mail.ru>
      Signed-off-by: NPeter Hurley <peter@hurleysoftware.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      ef8b9ddc
  3. 29 5月, 2014 1 次提交
    • M
      serial: uart: add hw flow control support configuration · 06aa82e4
      Murali Karicheri 提交于
      8250 uart driver currently supports only software assisted hw flow
      control. The software assisted hw flow control maintains a hw_stopped
      flag in the tty structure to stop and start transmission and use modem
      status interrupt for the event to drive the handshake signals. This is
      not needed if hw has flow control capabilities. This patch adds a
      DT attribute for enabling hw flow control for a uart port. Also skip
      stop and start if this flag is present in flag field of the port
      structure.
      Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
      CC: Rob Herring <robh+dt@kernel.org>
      CC: Pawel Moll <pawel.moll@arm.com>
      CC: Mark Rutland <mark.rutland@arm.com>
      CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
      CC: Kumar Gala <galak@codeaurora.org>
      CC: Randy Dunlap <rdunlap@infradead.org>
      CC: Jiri Slaby <jslaby@suse.cz>
      CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      06aa82e4
  4. 04 5月, 2014 1 次提交
  5. 25 4月, 2014 2 次提交
  6. 18 4月, 2014 1 次提交
  7. 17 4月, 2014 1 次提交
  8. 09 3月, 2014 1 次提交
  9. 01 3月, 2014 1 次提交
  10. 14 2月, 2014 1 次提交
  11. 08 1月, 2014 1 次提交
    • S
      serial: 8250: enable UART_BUG_NOMSR for Tegra · 3685f19e
      Stephen Warren 提交于
      Tegra chips have 4 or 5 identical UART modules embedded. UARTs C..E have
      their MODEM-control signals tied off to a static state. However UARTs A
      and B can optionally route those signals to/from package pins, depending
      on the exact pinmux configuration.
      
      When these signals are not routed to package pins, false interrupts may
      trigger either temporarily, or permanently, all while not showing up in
      the IIR; it will read as NO_INT. This will eventually lead to the UART
      IRQ being disabled due to unhandled interrupts. When this happens, the
      kernel may print e.g.:
      
          irq 68: nobody cared (try booting with the "irqpoll" option)
      
      In order to prevent this, enable UART_BUG_NOMSR. This prevents
      UART_IER_MSI from being enabled, which prevents the false interrupts
      from triggering.
      
      In practice, this is not needed under any of the following conditions:
      
      * On Tegra chips after Tegra30, since the HW bug has apparently been
        fixed.
      
      * On UARTs C..E since their MODEM control signals are tied to the correct
        static state which doesn't trigger the issue.
      
      * On UARTs A..B if the MODEM control signals are routed out to package
        pins, since they will then carry valid signals.
      
      However, we ignore these exceptions for now, since they are only relevant
      if a board actually hooks up more than a 4-wire UART, and no currently
      supported board does this. If we ever support a board that does, we can
      refine the algorithm that enables UART_BUG_NOMSR to take those exceptions
      into account, and/or read a flag from DT/... that indicates that the
      board has hooked up and pinmux'd more than a 4-wire UART.
      
      Reported-by: Olof Johansson <olof@lixom.net> # autotester
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      3685f19e
  12. 27 9月, 2013 1 次提交
  13. 01 8月, 2013 1 次提交
  14. 04 6月, 2013 1 次提交
  15. 26 3月, 2013 3 次提交
  16. 12 3月, 2013 2 次提交
  17. 30 1月, 2013 1 次提交
  18. 18 1月, 2013 1 次提交
  19. 16 1月, 2013 4 次提交
  20. 22 11月, 2012 7 次提交
  21. 25 10月, 2012 1 次提交
  22. 27 9月, 2012 2 次提交
  23. 22 9月, 2012 1 次提交
  24. 12 9月, 2012 1 次提交
  25. 27 7月, 2012 1 次提交
  26. 13 7月, 2012 1 次提交