1. 10 2月, 2017 1 次提交
    • J
      iommu: Introduce new 'struct iommu_device' · b0119e87
      Joerg Roedel 提交于
      This struct represents one hardware iommu in the iommu core
      code. For now it only has the iommu-ops associated with it,
      but that will be extended soon.
      
      The register/unregister interface is also added, as well as
      making use of it in the Intel and AMD IOMMU drivers.
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      b0119e87
  2. 21 12月, 2016 1 次提交
    • L
      ACPI / osl: Remove acpi_get_table_with_size()/early_acpi_os_unmap_memory() users · 6b11d1d6
      Lv Zheng 提交于
      This patch removes the users of the deprectated APIs:
       acpi_get_table_with_size()
       early_acpi_os_unmap_memory()
      The following APIs should be used instead of:
       acpi_get_table()
       acpi_put_table()
      
      The deprecated APIs are invented to be a replacement of acpi_get_table()
      during the early stage so that the early mapped pointer will not be stored
      in ACPICA core and thus the late stage acpi_get_table() won't return a
      wrong pointer. The mapping size is returned just because it is required by
      early_acpi_os_unmap_memory() to unmap the pointer during early stage.
      
      But as the mapping size equals to the acpi_table_header.length
      (see acpi_tb_init_table_descriptor() and acpi_tb_validate_table()), when
      such a convenient result is returned, driver code will start to use it
      instead of accessing acpi_table_header to obtain the length.
      
      Thus this patch cleans up the drivers by replacing returned table size with
      acpi_table_header.length, and should be a no-op.
      Reported-by: NDan Williams <dan.j.williams@intel.com>
      Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      6b11d1d6
  3. 30 10月, 2016 1 次提交
    • A
      iommu/vt-d: Fix IOMMU lookup for SR-IOV Virtual Functions · 1c387188
      Ashok Raj 提交于
      The VT-d specification (§8.3.3) says:
          ‘Virtual Functions’ of a ‘Physical Function’ are under the scope
          of the same remapping unit as the ‘Physical Function’.
      
      The BIOS is not required to list all the possible VFs in the scope
      tables, and arguably *shouldn't* make any attempt to do so, since there
      could be a huge number of them.
      
      This has been broken basically for ever — the VF is never going to match
      against a specific unit's scope, so it ends up being assigned to the
      INCLUDE_ALL IOMMU. Which was always actually correct by coincidence, but
      now we're looking at Root-Complex integrated devices with SR-IOV support
      it's going to start being wrong.
      
      Fix it to simply use pci_physfn() before doing the lookup for PCI devices.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NSainath Grandhi <sainath.grandhi@intel.com>
      Signed-off-by: NAshok Raj <ashok.raj@intel.com>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      1c387188
  4. 28 7月, 2016 1 次提交
    • L
      Add braces to avoid "ambiguous ‘else’" compiler warnings · 194dc870
      Linus Torvalds 提交于
      Some of our "for_each_xyz()" macro constructs make gcc unhappy about
      lack of braces around if-statements inside or outside the loop, because
      the loop construct itself has a "if-then-else" statement inside of it.
      
      The resulting warnings look something like this:
      
        drivers/gpu/drm/i915/i915_debugfs.c: In function ‘i915_dump_lrc’:
        drivers/gpu/drm/i915/i915_debugfs.c:2103:6: warning: suggest explicit braces to avoid ambiguous ‘else’ [-Wparentheses]
           if (ctx != dev_priv->kernel_context)
              ^
      
      even if the code itself is fine.
      
      Since the warning is fairly easy to avoid by adding a braces around the
      if-statement near the for_each_xyz() construct, do so, rather than
      disabling the otherwise potentially useful warning.
      
      (The if-then-else statements used in the "for_each_xyz()" constructs are
      designed to be inherently safe even with no braces, but in this case
      it's quite understandable that gcc isn't really able to tell that).
      
      This finally leaves the standard "allmodconfig" build with just a
      handful of remaining warnings, so new and valid warnings hopefully will
      stand out.
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      194dc870
  5. 13 7月, 2016 1 次提交
  6. 15 6月, 2016 1 次提交
    • R
      iommu/vt-d: Don't reject NTB devices due to scope mismatch · ffb2d1eb
      Roland Dreier 提交于
      On a system with an Intel PCIe port configured as an NTB device, iommu
      initialization fails with
      
          DMAR: Device scope type does not match for 0000:80:03.0
      
      This is because the DMAR table reports this device as having scope 2
      (ACPI_DMAR_SCOPE_TYPE_BRIDGE):
      
          [0A0h 0160   1]      Device Scope Entry Type : 02
          [0A1h 0161   1]                 Entry Length : 08
          [0A2h 0162   2]                     Reserved : 0000
          [0A4h 0164   1]               Enumeration ID : 00
          [0A5h 0165   1]               PCI Bus Number : 80
      
          [0A6h 0166   2]                     PCI Path : 03,00
      
      but the device has a type 0 PCI header:
      
          80:03.0 Bridge [0680]: Intel Corporation Device [8086:2f0d] (rev 02)
          00: 86 80 0d 2f 00 00 10 00 02 00 80 06 10 00 80 00
          10: 0c 00 c0 00 c0 38 00 00 0c 00 00 00 80 38 00 00
          20: 00 00 00 c8 00 00 10 c8 00 00 00 00 86 80 00 00
          30: 00 00 00 00 60 00 00 00 00 00 00 00 ff 01 00 00
      
      VT-d works perfectly on this system, so there's no reason to bail out
      on initialization due to this apparent scope mismatch.  Use the class
      0x0680 ("Other bridge device") as a heuristic for allowing DMAR
      initialization for non-bridge PCI devices listed with scope bridge.
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      ffb2d1eb
  7. 05 4月, 2016 2 次提交
  8. 01 3月, 2016 1 次提交
  9. 14 1月, 2016 1 次提交
  10. 07 1月, 2016 2 次提交
  11. 15 10月, 2015 1 次提交
  12. 03 8月, 2015 1 次提交
  13. 16 6月, 2015 1 次提交
  14. 24 4月, 2015 1 次提交
    • J
      iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit · 34742db8
      Jiang Liu 提交于
      Refine the interfaces to create IRQ for DMAR unit. It's a preparation
      for converting DMAR IRQ to hierarchical irqdomain on x86.
      
      It also moves dmar_alloc_hwirq()/dmar_free_hwirq() from irq_remapping.h
      to dmar.h. They are not irq_remapping specific.
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Cc: David Cohen <david.a.cohen@linux.intel.com>
      Cc: Sander Eikelenboom <linux@eikelenboom.it>
      Cc: David Vrabel <david.vrabel@citrix.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: iommu@lists.linux-foundation.org
      Cc: Vinod Koul <vinod.koul@intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
      Cc: Randy Dunlap <rdunlap@infradead.org>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Dimitri Sivanich <sivanich@sgi.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Fenghua Yu <fenghua.yu@intel.com>
      Cc: Joerg Roedel <joro@8bytes.org>
      Link: http://lkml.kernel.org/r/1428905519-23704-20-git-send-email-jiang.liu@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      34742db8
  15. 18 11月, 2014 4 次提交
  16. 02 10月, 2014 2 次提交
  17. 26 8月, 2014 1 次提交
  18. 19 8月, 2014 1 次提交
  19. 31 7月, 2014 1 次提交
  20. 04 7月, 2014 2 次提交
    • A
      iommu/vt-d: Make use of IOMMU sysfs support · a5459cfe
      Alex Williamson 提交于
      Register our DRHD IOMMUs, cross link devices, and provide a base set
      of attributes for the IOMMU.  Note that IRQ remapping support parses
      the DMAR table very early in boot, well before the iommu_class can
      reasonably be setup, so our registration is split between
      intel_iommu_init(), which occurs later, and alloc_iommu(), which
      typically occurs much earlier, but may happen at any time later
      with IOMMU hot-add support.
      
      On a typical desktop system, this provides the following (pruned):
      
      $ find /sys | grep dmar
      /sys/devices/virtual/iommu/dmar0
      /sys/devices/virtual/iommu/dmar0/devices
      /sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
      /sys/devices/virtual/iommu/dmar0/intel-iommu
      /sys/devices/virtual/iommu/dmar0/intel-iommu/cap
      /sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
      /sys/devices/virtual/iommu/dmar0/intel-iommu/address
      /sys/devices/virtual/iommu/dmar0/intel-iommu/version
      /sys/devices/virtual/iommu/dmar1
      /sys/devices/virtual/iommu/dmar1/devices
      /sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
      /sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
      /sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
      /sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
      /sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
      /sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
      ...
      /sys/devices/virtual/iommu/dmar1/intel-iommu
      /sys/devices/virtual/iommu/dmar1/intel-iommu/cap
      /sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
      /sys/devices/virtual/iommu/dmar1/intel-iommu/address
      /sys/devices/virtual/iommu/dmar1/intel-iommu/version
      /sys/class/iommu/dmar0
      /sys/class/iommu/dmar1
      
      (devices also link back to the dmar units)
      
      This makes address, version, capabilities, and extended capabilities
      available, just like printed on boot.  I've tried not to duplicate
      data that can be found in the DMAR table, with the exception of the
      address, which provides an easy way to associate the sysfs device with
      a DRHD entry in the DMAR.  It's tempting to add scopes and RMRR data
      here, but the full DMAR table is already exposed under /sys/firmware/
      and therefore already provides a way for userspace to learn such
      details.
      Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      a5459cfe
    • Y
      iommu/vt-d: Clear the redundant assignment in dmar_enable_qi · 435bbb46
      Yijing Wang 提交于
      __dmar_enable_qi() will initialize free_head,free_tail and
      free_cnt for q_inval. Remove the redundant initialization
      in dmar_enable_qi().
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      435bbb46
  21. 16 5月, 2014 2 次提交
  22. 15 4月, 2014 1 次提交
    • J
      iommu/vt-d: fix bug in matching PCI devices with DRHD/RMRR descriptors · 5ae0566a
      Jiang Liu 提交于
      Commit "59ce0515 iommu/vt-d: Update DRHD/RMRR/ATSR device scope
      caches when PCI hotplug happens" introduces a bug, which fails to
      match PCI devices with DMAR device scope entries if PCI path array
      in the entry has more than one level.
      
      For example, it fails to handle
      [1D2h 0466   1]      Device Scope Entry Type : 01
      [1D3h 0467   1]                 Entry Length : 0A
      [1D4h 0468   2]                     Reserved : 0000
      [1D6h 0470   1]               Enumeration ID : 00
      [1D7h 0471   1]               PCI Bus Number : 00
      [1D8h 0472   2]                     PCI Path : 1C,04
      [1DAh 0474   2]                     PCI Path : 00,02
      
      And cause DMA failure on HP DL980 as:
      DMAR:[fault reason 02] Present bit in context entry is clear
      dmar: DRHD: handling fault status reg 602
      dmar: DMAR:[DMA Read] Request device [02:00.2] fault addr 7f61e000
      Reported-and-tested-by: NDavidlohr Bueso <davidlohr@hp.com>
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      5ae0566a
  23. 01 4月, 2014 1 次提交
  24. 28 3月, 2014 1 次提交
  25. 26 3月, 2014 1 次提交
    • J
      iommu/vt-d: Check for NULL pointer in dmar_acpi_dev_scope_init() · 11f1a776
      Joerg Roedel 提交于
      When ir_dev_scope_init() is called via a rootfs initcall it
      will check for irq_remapping_enabled before it calls
      (indirectly) into dmar_acpi_dev_scope_init() which uses the
      dmar_tbl pointer without any checks.
      
      The AMD IOMMU driver also sets the irq_remapping_enabled
      flag which causes the dmar_acpi_dev_scope_init() function to
      be called on systems with AMD IOMMU hardware too, causing a
      boot-time kernel crash.
      Signed-off-by: NJoerg Roedel <joro@8bytes.org>
      11f1a776
  26. 24 3月, 2014 3 次提交
  27. 20 3月, 2014 2 次提交
  28. 05 3月, 2014 2 次提交
    • J
      iommu/vt-d: Unify the way to process DMAR device scope array · 2e455289
      Jiang Liu 提交于
      Now we have a PCI bus notification based mechanism to update DMAR
      device scope array, we could extend the mechanism to support boot
      time initialization too, which will help to unify and simplify
      the implementation.
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Signed-off-by: NJoerg Roedel <joro@8bytes.org>
      2e455289
    • J
      iommu/vt-d: Update DRHD/RMRR/ATSR device scope caches when PCI hotplug happens · 59ce0515
      Jiang Liu 提交于
      Current Intel DMAR/IOMMU driver assumes that all PCI devices associated
      with DMAR/RMRR/ATSR device scope arrays are created at boot time and
      won't change at runtime, so it caches pointers of associated PCI device
      object. That assumption may be wrong now due to:
      1) introduction of PCI host bridge hotplug
      2) PCI device hotplug through sysfs interfaces.
      
      Wang Yijing has tried to solve this issue by caching <bus, dev, func>
      tupple instead of the PCI device object pointer, but that's still
      unreliable because PCI bus number may change in case of hotplug.
      Please refer to http://lkml.org/lkml/2013/11/5/64
      Message from Yingjing's mail:
      after remove and rescan a pci device
      [  611.857095] dmar: DRHD: handling fault status reg 2
      [  611.857109] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff7000
      [  611.857109] DMAR:[fault reason 02] Present bit in context entry is clear
      [  611.857524] dmar: DRHD: handling fault status reg 102
      [  611.857534] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff6000
      [  611.857534] DMAR:[fault reason 02] Present bit in context entry is clear
      [  611.857936] dmar: DRHD: handling fault status reg 202
      [  611.857947] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff5000
      [  611.857947] DMAR:[fault reason 02] Present bit in context entry is clear
      [  611.858351] dmar: DRHD: handling fault status reg 302
      [  611.858362] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff4000
      [  611.858362] DMAR:[fault reason 02] Present bit in context entry is clear
      [  611.860819] IPv6: ADDRCONF(NETDEV_UP): eth3: link is not ready
      [  611.860983] dmar: DRHD: handling fault status reg 402
      [  611.860995] dmar: INTR-REMAP: Request device [[86:00.3] fault index a4
      [  611.860995] INTR-REMAP:[fault reason 34] Present field in the IRTE entry is clear
      
      This patch introduces a new mechanism to update the DRHD/RMRR/ATSR device scope
      caches by hooking PCI bus notification.
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Signed-off-by: NJoerg Roedel <joro@8bytes.org>
      59ce0515