1. 29 5月, 2013 3 次提交
    • G
      genirq: Generic chip: Handle separate mask registers · af80b0fe
      Gerlando Falauto 提交于
      There are cases where all irq_chip_type instances have separate mask
      registers, making a shared mask register cache unsuitable for the
      purpose.
      
      Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per
      chip mask pointer to the per chip private mask cache instead.
      
      [ tglx: Simplified code, renamed flag and massaged changelog ]
      Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Joey Oravec <joravec@drewtech.com>
      Cc: Lennert Buytenhek <kernel@wantstofly.org>
      Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
      Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
      Cc: Holger Brunck <Holger.Brunck@keymile.com>
      Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
      Acked-by: NGrant Likely <grant.likely@linaro.org>
      Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: devicetree-discuss@lists.ozlabs.org
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Ben Dooks <ben-linux@fluff.org>
      Cc: Gregory Clement <gregory.clement@free-electrons.com>
      Cc: Simon Guinot <simon@sequanux.org>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Cc: Jean-Francois Moine <moinejf@free.fr>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Rob Landley <rob@landley.net>
      Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
      Link: http://lkml.kernel.org/r/20130506142539.152569748@linutronix.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      af80b0fe
    • G
      genirq: Generic chip: Add support for per chip type mask cache · 899f0e66
      Gerlando Falauto 提交于
      Today the same interrupt mask cache (stored within struct irq_chip_generic)
      is shared between all the irq_chip_type instances. As there are instances
      where each irq_chip_type uses a distinct mask register (as it is the case
      for Orion SoCs), sharing a single mask cache may be incorrect.
      So add a distinct pointer for each irq_chip_type, which for now
      points to the original mask register within irq_chip_generic.
      So no functional changes here.
      
      [ tglx: Minor cosmetic tweaks ]
      Reported-by: NJoey Oravec <joravec@drewtech.com>
      Signed-off-by: NSimon Guinot <sguinot@lacie.com>
      Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
      Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Lennert Buytenhek <kernel@wantstofly.org>
      Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
      Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
      Cc: Holger Brunck <Holger.Brunck@keymile.com>
      Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
      Acked-by: NGrant Likely <grant.likely@linaro.org>
      Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: devicetree-discuss@lists.ozlabs.org
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Ben Dooks <ben-linux@fluff.org>
      Cc: Gregory Clement <gregory.clement@free-electrons.com>
      Cc: Simon Guinot <simon@sequanux.org>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Cc: Jean-Francois Moine <moinejf@free.fr>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Rob Landley <rob@landley.net>
      Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
      Link: http://lkml.kernel.org/r/20130506142539.082226607@linutronix.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      899f0e66
    • G
      genirq: Generic chip: Remove the local cur_regs() function · cfeaa93f
      Gerlando Falauto 提交于
      Since we already have an irq_data_get_chip_type() function which returns
      a pointer to irq_chip_type, use that instead of cur_regs().
      Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Joey Oravec <joravec@drewtech.com>
      Cc: Lennert Buytenhek <kernel@wantstofly.org>
      Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
      Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
      Cc: Holger Brunck <Holger.Brunck@keymile.com>
      Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
      Acked-by: NGrant Likely <grant.likely@linaro.org>
      Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: devicetree-discuss@lists.ozlabs.org
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Ben Dooks <ben-linux@fluff.org>
      Cc: Gregory Clement <gregory.clement@free-electrons.com>
      Cc: Simon Guinot <simon@sequanux.org>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Cc: Jean-Francois Moine <moinejf@free.fr>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Rob Landley <rob@landley.net>
      Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
      Link: http://lkml.kernel.org/r/20130506142539.010164766@linutronix.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      cfeaa93f
  2. 01 11月, 2011 1 次提交
  3. 24 10月, 2011 1 次提交
  4. 26 7月, 2011 1 次提交
  5. 08 7月, 2011 1 次提交
    • S
      genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd) · 659fb32d
      Simon Guinot 提交于
      This fixes a regression introduced by e59347a1 "arm: orion:
      Use generic irq chip".
      
      Depending on the device, interrupts acknowledgement is done by setting
      or by clearing a dedicated register. Replace irq_gc_ack() with some
      {set,clr}_bit variants allows to handle both cases.
      
      Note that this patch affects the following SoCs: Davinci, Samsung and
      Orion. Except for this last, the change is minor: irq_gc_ack() is just
      renamed into irq_gc_ack_set_bit().
      
      For the Orion SoCs, the edge GPIO interrupts support is currently
      broken. irq_gc_ack() try to acknowledge a such interrupt by setting
      the corresponding cause register bit. The Orion GPIO device expect the
      opposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.
      
      Tested on Network Space v2.
      Reported-by: NJoey Oravec <joravec@drewtech.com>
      Signed-off-by: NSimon Guinot <sguinot@lacie.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      659fb32d
  6. 23 4月, 2011 2 次提交