Add hwmod data for RTC
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NSebastian Andrzej Siewior <sebastian@breakpoint.cc>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Tested-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Tested-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This module is needed for the SATA and PCIe PHYs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

DMA interrupts are now available in of, and the definitions are
duplicates in hwmod. This prevents us from dynamically allocating
interrupt resources for dma from devicetree.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the hwmod data for the 13 instances of the system mailbox
IP in DRA7 SoC. The patch is needed for performing a soft-reset
while configuring the respective mailbox instance, otherwise is
a non-essential change for functionality. The modules are smart
idled on reset, and the IP module mode is hardware controlled.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Get rid of optional clock as that is now managed by the
AHCI platform driver.

Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Reviewed-by: NRajendra Nayak <rnayak@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.

Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.

CC: Benoît Cousson <bcousson@baylibre.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The spinlock module's SYSCONFIG register on DRA7xx does not
support smart wakeup, and also does not have the CLKACTIVITY
field. The sysc data for spinlock module has been appropriately
fixed up to reflect the same.

Cc: Ambresh K <ambresh@ti.com>
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

With commit '7dedd346: ARM: OMAP2+: hwmod: Fix a crash in _setup_reset() with
 DEBUG_LL' we moved from parsing cmdline to identify uart used for earlycon
to using the requsite hwmod CONFIG_DEBUG_OMAPxUARTy FLAGS.

On DRA7 though, we seem to be missing this flag, and atleast on the DRA7 EVM
where we use uart1 for console, boot fails with DEBUG_LL enabled.
Reported-by: NLokesh Vutla <lokeshvutla@ti.com>
Tested-by:  Lokesh Vutla <lokeshvutla@ti.com> # on a different base
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Fixes: 7dedd346 ("ARM: OMAP2+: hwmod: Fix a crash in _setup_reset() with DEBUG_LL")
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Adding the hwmod data for DRA7XX platforms.
Signed-off-by: NAmbresh K <ambresh@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>