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  1. 24 11月, 2014 1 次提交
  3. 22 11月, 2014 1 次提交
  5. 12 11月, 2014 1 次提交
  7. 11 11月, 2014 6 次提交
  9. 09 9月, 2014 3 次提交
  11. 26 8月, 2014 1 次提交
    • N
      ARM: dts: DRA7: fix interrupt-cells for GPIO · e49d519c
      由 Nishanth Menon 提交于 
      GPIO modules are also interrupt sources. However, they require both the
GPIO number and IRQ type to function properly.

By declaring that GPIO uses interrupt-cells=<1>, we essentially do not
allow users of the nodes to use the interrupt property appropritely.

With this change, the following now works:

interrupt-parent = <&gpio6>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;

Fixes: 6e58b8f1 ('ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board')
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      e49d519c
  13. 15 7月, 2014 4 次提交
    • S
      ARM: dts: DRA7: Add mailbox nodes · 38baefb3
      由 Suman Anna 提交于 
      DRA7xx has 13 system mailboxes, and is present on both the
DRA72x and DRA74x family of SoCs. Add the DT nodes for all
these 13 mailboxes. Except for mailbox 1, all other mailboxes
do not have interrupts mapped into the MPU GIC by default.

All the mailboxes have been disabled and the interrupts
property information is left out intentionally for now,
because of the dependencies against the crossbar driver.
These mailboxes can be enabled when a usecase arises
and the crossbar driver dependencies are met.

NOTE: The mailbox 1 has different number of mailbox fifos
and IP interrupts compared to the remaining 12 mailboxes.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      38baefb3
    • K
      ARM: dts: dra7: Add dt data for PCIe controller · 18dcd79d
      由 Kishon Vijay Abraham I 提交于 
      Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      18dcd79d
    • K
      ARM: dts: dra7: Add dt data for PCIe PHY · 692df0ef
      由 Kishon Vijay Abraham I 提交于 
      Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0
describes the PCIe PHY subsystem-related components integrated in the device.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      692df0ef
    • K
      ARM: dts: dra7: Add dt data for PCIe PHY control module · d1ff66b5
      由 Kishon Vijay Abraham I 提交于 
      Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt

Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      d1ff66b5
  15. 09 7月, 2014 2 次提交
    • R
      ARM: dts: dra7: add crossbar device binding · a46631c4
      由 R Sricharan 提交于 
      There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.

Here, adding a new crossbar device node and replacing all the peripheral
interrupt numbers with its fixed crossbar input lines.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      a46631c4
    • R
      ARM: dts: dra7: add routable-irqs property for gic node · 51300633
      由 R Sricharan 提交于 
      There is a IRQ crossbar device in the soc, which maps the
irq requests from the peripherals to the mpu interrupt
controller's inputs. The gic provides the support for such
IPs in the form of routable-irqs. So adding the property
here to gic node.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      51300633
  17. 17 6月, 2014 1 次提交
  19. 16 6月, 2014 1 次提交
  21. 20 5月, 2014 1 次提交
  23. 15 5月, 2014 2 次提交
  25. 07 5月, 2014 2 次提交
  27. 06 5月, 2014 1 次提交
  29. 19 4月, 2014 2 次提交
  31. 06 3月, 2014 1 次提交
  33. 05 3月, 2014 1 次提交
  35. 03 3月, 2014 1 次提交
  37. 01 3月, 2014 2 次提交
  39. 18 1月, 2014 1 次提交
  41. 22 10月, 2013 3 次提交
  43. 08 10月, 2013 2 次提交