1. 04 10月, 2006 1 次提交
    • E
      [PATCH] genirq: i386 irq: Remove the msi assumption that irq == vector · ace80ab7
      Eric W. Biederman 提交于
      This patch removes the change in behavior of the irq allocation code when
      CONFIG_PCI_MSI is defined.  Removing all instances of the assumption that irq
      == vector.
      
      create_irq is rewritten to first allocate a free irq and then to assign that
      irq a vector.
      
      assign_irq_vector is made static and the AUTO_ASSIGN case which allocates an
      vector not bound to an irq is removed.
      
      The ioapic vector methods are removed, and everything now works with irqs.
      
      The definition of NR_IRQS no longer depends on CONFIG_PCI_MSI
      
      [akpm@osdl.org: cleanup]
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      ace80ab7
  2. 26 9月, 2006 6 次提交
  3. 19 8月, 2006 1 次提交
  4. 01 7月, 2006 1 次提交
  5. 22 6月, 2006 1 次提交
  6. 14 6月, 2006 1 次提交
    • B
      ACPI: ACPICA 20060331 · 793c2388
      Bob Moore 提交于
      Implemented header file support for the following
      additional ACPI tables: ASF!, BOOT, CPEP, DBGP, MCFG, SPCR,
      SPMI, TCPA, and WDRT. With this support, all current and
      known ACPI tables are now defined in the ACPICA headers and
      are available for use by device drivers and other software.
      
      Implemented support to allow tables that contain ACPI
      names with invalid characters to be loaded. Previously,
      this would cause the table load to fail, but since
      there are several known cases of such tables on
      existing machines, this change was made to enable
      ACPI support for them. Also, this matches the
      behavior of the Microsoft ACPI implementation.
      https://bugzilla.novell.com/show_bug.cgi?id=147621
      
      Fixed a couple regressions introduced during the memory
      optimization in the 20060317 release. The namespace
      node definition required additional reorganization and
      an internal datatype that had been changed to 8-bit was
      restored to 32-bit. (Valery Podrezov)
      
      Fixed a problem where a null pointer passed to
      acpi_ut_delete_generic_state() could be passed through
      to acpi_os_release_object which is unexpected. Such
      null pointers are now trapped and ignored, matching
      the behavior of the previous implementation before the
      deployment of acpi_os_release_object().  (Valery Podrezov,
      Fiodor Suietov)
      
      Fixed a memory mapping leak during the deletion of
      a SystemMemory operation region where a cached memory
      mapping was not deleted. This became a noticeable problem
      for operation regions that are defined within frequently
      used control methods. (Dana Meyers)
      
      Reorganized the ACPI table header files into two main
      files: one for the ACPI tables consumed by the ACPICA core,
      and another for the miscellaneous ACPI tables that are
      consumed by the drivers and other software. The various
      FADT definitions were merged into one common section and
      three different tables (ACPI 1.0, 1.0+, and 2.0)
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      793c2388
  7. 31 5月, 2006 1 次提交
  8. 16 5月, 2006 1 次提交
  9. 04 5月, 2006 1 次提交
  10. 02 5月, 2006 1 次提交
  11. 19 4月, 2006 1 次提交
  12. 11 4月, 2006 1 次提交
  13. 10 4月, 2006 1 次提交
  14. 27 3月, 2006 2 次提交
  15. 09 3月, 2006 1 次提交
    • A
      [PATCH] i386: port ATI timer fix from x86_64 to i386 II · f9262c12
      Andi Kleen 提交于
      ATI chipsets tend to generate double timer interrupts for the local APIC
      timer when both the 8254 and the IO-APIC timer pins are enabled.  This is
      because they route it to both and the result is anded together and the CPU
      ends up processing it twice.
      
      This patch changes check_timer to disable the 8254 routing for interrupt 0.
      
      I think it would be safe on all chipsets actually (i tested it on a couple
      and it worked everywhere) and Windows seems to do it in a similar way, but
      to be conservative this patch only enables this mode on ATI (and adds
      options to enable/disable too)
      
      Ported over from a similar x86-64 change.
      
      I reused the ACPI earlyquirk infrastructure for the ATI bridge check, but
      tweaked it a bit to work even without ACPI.
      
      Inspired by a patch from Chuck Ebbert, but redone.
      
      Cc: Chuck Ebbert <76306.1226@compuserve.com>
      Cc: "Brown, Len" <len.brown@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f9262c12
  16. 28 2月, 2006 1 次提交
  17. 27 2月, 2006 1 次提交
  18. 05 2月, 2006 1 次提交
  19. 12 1月, 2006 1 次提交
  20. 28 12月, 2005 1 次提交
  21. 01 12月, 2005 1 次提交
  22. 21 11月, 2005 1 次提交
  23. 15 11月, 2005 2 次提交
    • S
      [PATCH] x86_64: Unmap NULL during early bootup · f6c2e333
      Siddha, Suresh B 提交于
      We should zap the low mappings, as soon as possible, so that we can catch
      kernel bugs more effectively. Previously early boot had NULL mapped
      and didn't trap on NULL references.
      
      This patch introduces boot_level4_pgt, which will always have low identity
      addresses mapped.  Druing boot, all the processors will use this as their
      level4 pgt.  On BP, we will switch to init_level4_pgt as soon as we enter C
      code and zap the low mappings as soon as we are done with the usage of
      identity low mapped addresses.  On AP's we will zap the low mappings as
      soon as we jump to C code.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NAshok Raj <ashok.raj@intel.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f6c2e333
    • J
      [PATCH] i386/x86-64: Share interrupt vectors when there is a large number of interrupt sources · 6004e1b7
      James Cleverdon 提交于
      Here's a patch that builds on Natalie Protasevich's IRQ compression
      patch and tries to work for MPS boots as well as ACPI.  It is meant for
      a 4-node IBM x460 NUMA box, which was dying because it had interrupt
      pins with GSI numbers > NR_IRQS and thus overflowed irq_desc.
      
      The problem is that this system has 270 GSIs (which are 1:1 mapped with
      I/O APIC RTEs) and an 8-node box would have 540.  This is much bigger
      than NR_IRQS (224 for both i386 and x86_64).  Also, there aren't enough
      vectors to go around.  There are about 190 usable vectors, not counting
      the reserved ones and the unused vectors at 0x20 to 0x2F.  So, my patch
      attempts to compress the GSI range and share vectors by sharing IRQs.
      
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@unisys.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      6004e1b7
  24. 01 10月, 2005 1 次提交
  25. 27 9月, 2005 1 次提交
  26. 05 9月, 2005 1 次提交
  27. 26 8月, 2005 1 次提交
  28. 25 8月, 2005 2 次提交
  29. 05 8月, 2005 3 次提交
  30. 28 6月, 2005 1 次提交