1. 28 9月, 2005 21 次提交
  2. 27 9月, 2005 15 次提交
  3. 26 9月, 2005 3 次提交
    • D
      [SPARC64]: Probe D/I/E-cache config and use. · 80dc0d6b
      David S. Miller 提交于
      At boot time, determine the D-cache, I-cache and E-cache size and
      line-size.  Use them in cache flushes when appropriate.
      
      This change was motivated by discovering that the D-cache on
      UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
      Cheetah error handlers were assuming a 32K size.
      
      There are still some pieces of code that are hard coding things and
      will need to be fixed up at some point.
      
      While we're here, fix the D-cache and I-cache parity error handlers
      to run with interrupts disabled, and when the trap occurs at trap
      level > 1 log the event via a counter displayed in /proc/cpuinfo.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      80dc0d6b
    • P
      powerpc: Merge enough to start building in arch/powerpc. · 14cf11af
      Paul Mackerras 提交于
      This creates the directory structure under arch/powerpc and a bunch
      of Kconfig files.  It does a first-cut merge of arch/powerpc/mm,
      arch/powerpc/lib and arch/powerpc/platforms/powermac.  This is enough
      to build a 32-bit powermac kernel with ARCH=powerpc.
      
      For now we are getting some unmerged files from arch/ppc/kernel and
      arch/ppc/syslib, or arch/ppc64/kernel.  This makes some minor changes
      to files in those directories and files outside arch/powerpc.
      
      The boot directory is still not merged.  That's going to be interesting.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      14cf11af
    • D
      [SPARC64]: Add CONFIG_DEBUG_PAGEALLOC support. · 56425306
      David S. Miller 提交于
      The trick is that we do the kernel linear mapping TLB miss starting
      with an instruction sequence like this:
      
      	ba,pt		%xcc, kvmap_load
      	 xor		%g2, %g4, %g5
      
      succeeded by an instruction sequence which performs a full page table
      walk starting at swapper_pg_dir.
      
      We first take over the trap table from the firmware.  Then, using this
      constant PTE generation for the linear mapping area above, we build
      the kernel page tables for the linear mapping.
      
      After this is setup, we patch that branch above into a "nop", which
      will cause TLB misses to fall through to the full page table walk.
      
      With this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      56425306
  4. 25 9月, 2005 1 次提交