Add vcc_mmc1 fixed regulator to remove the 'no vmmc regulator found' warning
when probing the mmc1 device.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add fixed regulator for vmmc0 and attach the vmmc for it to the mmc0
node on the SAM5D3 Xplained board. This will remove the following
warning from the kernel:

atmel_mci f0000000.mmc: No vmmc regulator found

Note, atmel_defconfig will need fixed regulator support enabled if this
is to be used properly.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
[use a fixed regulator instead of gpio one]
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The SAM5D3 Xplained device tree is missing the vqmmc node which is
tied to 3.3V on the board. Add this to avoid the kernel warning that
there is no vqmmc node.

atmel_mci f0000000.mmc: No vqmmc regulator found
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The mmc1 channel is not populated on the SAM5D3 Xplained board, however
it is enabled and therefore the driver is attaching to it.

The node configuration for mmc1 is missing, so add an mmc1 node in the
device tree and set its status to disabled. Also add the vmmc and the
necessary slot configuration if this node were enabled to avoid the following
warnings from the driver:

atmel_mci f8000000.mmc: No vmmc regulator found
atmel_mci f8000000.mmc: No vqmmc regulator found
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

commit 111573cc ("mtd: atmel_nand: check NFC busy flag by HSMC_SR
instead of NFC cmd regs")
check NFC busy by nfc SR instead of NFC cmd regs. So we don't need to
map NFC cmd registers to include NFCBUSY bit.
That means we only need map 0x08000000 instead of 0x10000000 for NFC
cmd regs.

This patch reduce the NFC cmd regs map for sama5d3 & sama5d4.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Update the pinctrl ranges property to support pioD controller whose
mapping is not contiguous with other pio controllers. Without this
update, getting resource will fail, then pinctrl probe will fail too
because there is a missing pio controller.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Specify the phy address on macb0 node aka GEM.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Route SPI1 on the Arduino "in the middle" spi connector.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add sama5d4 spi1, spi2 dt nodes & pinctrl.
Signed-off-by: NSuchang Ko <suchangko@samul.kr>
[nicolas.ferre@atmel.com: split patch, reorder & whitespace fixes]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The current GPLv2 only licensing on this dts makes it very impractical
for other software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense
this dts under a GPLv2/X11 dual-license.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The current GPLv2 only licensing on this dtsi makes it very impractical
for other software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense
this dtsi under a GPLv2/X11 dual-license.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The current GPLv2 only licensing on this dts makes it very impractical
for other software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense
this dts under a GPLv2/X11 dual-license.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The current GPLv2 only licensing on this dtsi makes it very impractical
for other software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense
this dtsi under a GPLv2/X11 dual-license.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The current GPLv2 only licensing on this dts makes it very impractical
for other software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense
this dts under a GPLv2/X11 dual-license.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The current GPLv2 only licensing on this dtsi makes it very impractical
for other software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense
this dtsi under a GPLv2/X11 dual-license.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NJisheng Zhang <jszhang@marvell.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Add basic support for Hitex LPC4350 Evaluation Board. Board
features a LPC4350 Soc, 8 MB SDRAM, 8 MB SPI Flash, USB and
Ethernet.

More information can be found on:
http://www.hitex.com/index.php?id=3212Signed-off-by: NAriel D'Alessandro <ariel.dalessandro@gmail.com>
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Adds basic support for Embedded Artists' LPC4357 Developer's Kit. Board
features a LPC4357 Soc, 32 MB SDRAM, 128 MB NAND Flash, 16 MB SPI
Flash, USB and Ethernet.

More information can be found on:
http://www.embeddedartists.com/products/kits/lpc4357_kit.phpSigned-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

NXP LPC18xx/43xx SoCs are very similar devices and should be able to
share a common base (lpc18xx.dtsi). Diffences between the devices are
put in a dtsi which is specific to that device.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The Ux500 like other Cortex-A9 SoC's has a Snoop Control
Unit (SCU) and a Watchdog in the same address range as
the local timers. Add these to the SoC device tree.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch fixes a regression where serial is enabled by the first
(board) DTSI, then disabled by the second (SoC) file.  To enable
serial and keep it enabled, we need to include the file which enables
it last.

Reported-by: LAVA [via Peter Griffin <peter.griffin@linaro.org>]
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses.  These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits.  The bits in the bus address mean:

From the VideoCore processor:
0x0... L1 and L2 cache allocating and coherent
0x4... L1 non-allocating, but coherent. L2 allocating and coherent
0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent

From the GPU peripherals (note: all peripherals bypass the L1
cache. The ARM will see this view once through the VC MMU):
0x0... Do not use
0x4... L1 non-allocating, and incoherent. L2 allocating and coherent.
0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent

The 2835 firmware always configures the MMU to turn ARM physical
addresses with 0x0 top bits to 0x4, meaning present in L2 but
incoherent with L1.  However, any bus addresses we were generating in
the kernel to be passed to a device had 0x0 bits.  That would be a
reserved (possibly totally incoherent) value if sent to a GPU
peripheral like USB, or L1 allocating if sent to the VC (like a
firmware property request).  By setting dma-ranges, all of the devices
below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and
friends return addresses with 0x4 bits and avoid cache incoherency.

This matches the behavior in the downstream 2708 kernel (see
BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h).
Signed-off-by: NEric Anholt <eric@anholt.net>
Tested-by: NNoralf Trønnes <noralf@tronnes.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Device tree node names should contain the node's reg property address value.
The i2c0 node was apparently forgotten in commit 25b2f1bd (ARM: bcm2835:
node name unit address cleanup).
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch converts all bcm2835 dts and dtsi files to use the pinctrl
header file.
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add a "brcm,bcm6328-timer" and "syscon-reboot" nodes to allow the
generic syscon-reboot driver to reset a BCM63138 SoC.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Enable NAND support for Broadcom Cygnus SoC
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Update bcm63138.dtsi with the following:

- enable-method for both CPU nodes
- brcm,bcm63138-bootlut node
- resets properties to point to the correct PMB controller to release
  the secondary CPU from reset
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add the two BCM63138 PMB busses nodes found on this System-on-a-Chip as
described in their corresponding binding document.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add the dts node for the A9 SCU.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

This adds the device tree data for the LIS331DL and the
AK8974 magnetometer to the STUIB board device tree include
file.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The ST sensors on the Ux500 boards were not utilizing the IRQs
for data ready sample triggers. Enable this by assigning the
right GPIO lines and interrupt lines (when the GPIO lines are
used for IRQs) to the accelerometer, gyro and magnetometer
sensors.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>