1. 19 5月, 2015 1 次提交
    • J
      genirq: Introduce irq_set_vcpu_affinity() to target an interrupt to a VCPU · 0a4377de
      Jiang Liu 提交于
      With Posted-Interrupts support in Intel CPU and IOMMU, an external
      interrupt from assigned-devices could be directly delivered to a
      virtual CPU in a virtual machine. Instead of hacking KVM and Intel
      IOMMU drivers, we propose a platform independent interface to target
      an interrupt to a specific virtual CPU in a virtual machine, or set
      virtual CPU affinity for an interrupt.
      
      By adopting this new interface and the hierarchy irqdomain, we could
      easily support posted-interrupts on Intel platforms, and also provide
      flexible enough interfaces for other platforms to support similar
      features.
      
      Here is the usage scenario for this interface:
      Guest update MSI/MSI-X interrupt configuration
              -->QEMU and KVM handle this
              -->KVM call this interface (passing posted interrupts descriptor
                 and guest vector)
              -->irq core will transfer the control to IOMMU
              -->IOMMU will do the real work of updating IRTE (IRTE has new
                 format for VT-d Posted-Interrupts)
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Signed-off-by: NFeng Wu <feng.wu@intel.com>
      Link: http://lkml.kernel.org/r/1432026437-16560-2-git-send-email-feng.wu@intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      0a4377de
  2. 18 5月, 2015 1 次提交
    • S
      genirq: Add irq_chip_(enable/disable)_parent · 3cfeffc2
      Stefan Agner 提交于
      Add helper irq_chip_enable_parent and irq_chip_disable_parent. The
      helper implement the default behavior in case irq_enable or irq_disable
      is not implemented for the parent interrupt chip, which is calling the
      irq_mask or irq_unmask respectively.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Cc: marc.zyngier@arm.com
      Cc: linux@arm.linux.org.uk
      Cc: u.kleine-koenig@pengutronix.de
      Cc: olof@lixom.net
      Cc: arnd@arndb.de
      Cc: daniel.lezcano@linaro.org
      Cc: mark.rutland@arm.com
      Cc: pawel.moll@arm.com
      Cc: robh+dt@kernel.org
      Cc: ijc+devicetree@hellion.org.uk
      Cc: galak@codeaurora.org
      Cc: mcoquelin.stm32@gmail.com
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: shawn.guo@linaro.org
      Cc: kernel@pengutronix.de
      Cc: jason@lakedaemon.net
      Link: http://lkml.kernel.org/r/1431769465-26867-3-git-send-email-stefan@agner.chSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      3cfeffc2
  3. 15 3月, 2015 1 次提交
  4. 23 11月, 2014 5 次提交
    • M
      genirq: Work around __irq_set_handler vs stacked domains ordering issues · f86eff22
      Marc Zyngier 提交于
      With the introduction of stacked domains, we have the issue that,
      depending on where in the stack this is called, __irq_set_handler
      will succeed or fail: If this is called from the inner irqchip,
      __irq_set_handler() will fail, as it will look at the outer domain
      as the (desc->irq_data.chip == &no_irq_chip) test fails (we haven't
      set the top level yet).
      
      This patch implements the following: "If there is at least one
      valid irqchip in the domain, it will probably sort itself out".
      This is clearly not ideal, but it is far less confusing then
      crashing because the top-level domain is not up yet.
      
      [ tglx: Added comment and a protection against chained interrupts in
        	that context ]
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Link: http://lkml.kernel.org/r/1416048553-29289-3-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      f86eff22
    • J
      genirq: Introduce irq_chip.irq_compose_msi_msg() to support stacked irqchip · 515085ef
      Jiang Liu 提交于
      Add callback irq_compose_msi_msg to struct irq_chip, which will be used
      to support stacked irqchip.
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      515085ef
    • Y
      genirq: Add more helper functions to support stacked irq_chip · 56e8abab
      Yingjoe Chen 提交于
      Add more helper function for stacked irq_chip to just call parent's
      function.
      Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Matthias Brugger <matthias.bgg@gmail.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Gran Likely <grant.likely@linaro.org>
      Cc: Boris BREZILLON <boris.brezillon@free-electrons.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Cc: <srv_heupstream@mediatek.com>
      Cc: <yingjoe.chen@gmail.com>
      Cc: <hc.yen@mediatek.com>
      Cc: <eddie.huang@mediatek.com>
      Cc: <nathan.chung@mediatek.com>
      Cc: <yh.chen@mediatek.com>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Link: http://lkml.kernel.org/r/1415893029-2971-3-git-send-email-yingjoe.chen@mediatek.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      56e8abab
    • J
      genirq: Introduce helper functions to support stacked irq_chip · 85f08c17
      Jiang Liu 提交于
      Now we already support hierarchy irq_data, so introduce several helpers
      to support stacked irq_chips.
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      85f08c17
    • J
      irqdomain: Introduce new interfaces to support hierarchy irqdomains · f8264e34
      Jiang Liu 提交于
      We plan to use hierarchy irqdomain to suppport CPU vector assignment,
      interrupt remapping controller, IO-APIC controller, MSI interrupt
      and hypertransport interrupt etc on x86 platforms. So extend irqdomain
      interfaces to support hierarchy irqdomain.
      
      There are already many clients of current irqdomain interfaces.
      To minimize the changes, we choose to introduce new version 2 interfaces
      to support hierarchy instead of extending existing irqdomain interfaces.
      
      According to Thomas's suggestion, the most important design decision is
      to build hierarchy struct irq_data to support hierarchy irqdomain, so
      hierarchy irqdomain related data could be saved in struct irq_data.
      With support of hierarchy irq_data, we could also support stacked
      irq_chips. This is most useful in case of set_affinity().
      
      The new hierarchy irqdomain introduces following interfaces:
      1) irq_domain_alloc_irqs()/irq_domain_free_irqs(): allocate/release IRQ
         and related resources.
      2) __irq_domain_alloc_irqs(): a special version to support legacy IRQs.
      3) irq_domain_activate_irq()/irq_domain_deactivate_irq(): program
         interrupt controllers to activate/deactivate interrupt.
      
      There are also several help functions to ease irqdomain implemenations:
      1) irq_domain_get_irq_data(): get irq_data associated with a specific
         irqdomain.
      2) irq_domain_set_hwirq_and_chip(): save irqdomain specific data into
         irq_data.
      3) irq_domain_alloc_irqs_parent()/irq_domain_free_irqs_parent(): invoke
         parent irqdomain's alloc/free callbacks.
      
      We also changed irq_startup()/irq_shutdown() to invoke
      irq_domain_activate_irq()/irq_domain_deactivate_irq() to program
      interrupt controller when start/stop interrupts.
      
      [ tglx: Folded parts of the later patch series in ]
      Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
      Cc: Yijing Wang <wangyijing@huawei.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      f8264e34
  5. 25 9月, 2014 1 次提交
  6. 01 9月, 2014 3 次提交
  7. 27 8月, 2014 1 次提交
  8. 26 8月, 2014 1 次提交
  9. 16 5月, 2014 1 次提交
  10. 14 3月, 2014 1 次提交
  11. 18 10月, 2013 1 次提交
  12. 29 5月, 2013 1 次提交
  13. 25 1月, 2013 1 次提交
    • A
      x86/MSI: Support multiple MSIs in presense of IRQ remapping · 51906e77
      Alexander Gordeev 提交于
      The MSI specification has several constraints in comparison with
      MSI-X, most notable of them is the inability to configure MSIs
      independently. As a result, it is impossible to dispatch
      interrupts from different queues to different CPUs. This is
      largely devalues the support of multiple MSIs in SMP systems.
      
      Also, a necessity to allocate a contiguous block of vector
      numbers for devices capable of multiple MSIs might cause a
      considerable pressure on x86 interrupt vector allocator and
      could lead to fragmentation of the interrupt vectors space.
      
      This patch overcomes both drawbacks in presense of IRQ remapping
      and lets devices take advantage of multiple queues and per-IRQ
      affinity assignments.
      Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Matthew Wilcox <willy@linux.intel.com>
      Cc: Jeff Garzik <jgarzik@pobox.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/c8bd86ff56b5fc118257436768aaa04489ac0a4c.1353324359.git.agordeev@redhat.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      51906e77
  14. 01 11月, 2012 1 次提交
    • T
      genirq: Provide means to retrigger parent · 293a7a0a
      Thomas Gleixner 提交于
      Attempts to retrigger nested threaded IRQs currently fail because they
      have no primary handler. In order to support retrigger of nested
      IRQs, the parent IRQ needs to be retriggered.
      
      To fix, when an IRQ needs to be resent, if the interrupt has a parent
      IRQ and runs in the context of the parent IRQ, then resend the parent.
      
      Also, handle_nested_irq() needs to clear the replay flag like the
      other handlers, otherwise check_irq_resend() will set it and it will
      never be cleared.  Without clearing, it results in the first resend
      working fine, but check_irq_resend() returning early on subsequent
      resends because the replay flag is still set.
      
      Problem discovered on ARM/OMAP platforms where a nested IRQ that's
      also a wakeup IRQ happens late in suspend and needed to be retriggered
      during the resume process.
      
      [khilman@ti.com: changelog edits, clear IRQS_REPLAY in handle_nested_irq()]
      Reported-by: NKevin Hilman <khilman@ti.com>
      Tested-by: NKevin Hilman <khilman@ti.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Link: http://lkml.kernel.org/r/1350425269-11489-1-git-send-email-khilman@deeprootsystems.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      293a7a0a
  15. 21 8月, 2012 1 次提交
  16. 25 5月, 2012 1 次提交
    • N
      genirq: Add IRQS_PENDING for nested and simple irq · 23812b9d
      Ning Jiang 提交于
      Every interrupt which is an active wakeup source needs the ability to
      abort suspend if there is a pending irq. Right now only edge and level
      irqs can do that.
      
                  |
             +---------+
             |   INTC  |
             +---------+
                     | GPIO_IRQ
                  +------------+
                  |  gpio-exp  |
                  +------------+
                    |        |
               GPIO0_IRQ  GPIO1_IRQ
      
      In the above diagram, gpio expander has irq number GPIO_IRQ, it is
      connected with two sub GPIO pins, GPIO0 and GPIO1.
      
      During suspend, we set IRQF_NO_SUSPEND for GPIO_IRQ so that gpio
      expander driver can handle the sub irq GPIO0_IRQ and GPIO1_IRQ, and
      these two irqs themselves can further be handled by simple or nested
      irq in some drivers(typically gpio and mfd driver). If they are used
      as wakeup sources during suspend, we want them to be able to abort
      suspend too.
      
      Setting IRQS_PENDING flag in handle_nested_irq() and handle_simple_irq()
      when the irq is disabled allows check_wakeup_irqs() to identify such
      irqs as source for aborting suspend.
      Signed-off-by: NNing Jiang <ning.n.jiang@gmail.com>
      Cc: rjw@sisk.pl
      Link: http://lkml.kernel.org/r/CAH3Oq6T905%2B3fkF43NAMMFvJvq7dsk_so6T2vQ8ZJrA5xiU3YA@mail.gmail.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      23812b9d
  17. 15 5月, 2012 1 次提交
    • J
      genirq: export handle_edge_irq() and irq_to_desc() · 3911ff30
      Jiri Kosina 提交于
      Export handle_edge_irq() and irq_to_desc() to modules to allow them to
      do things such as
      
      	__irq_set_handler_locked(...., handle_edge_irq);
      
      This fixes
      
      	ERROR: "handle_edge_irq" [drivers/gpio/gpio-pch.ko] undefined!
      	ERROR: "irq_to_desc" [drivers/gpio/gpio-pch.ko] undefined!
      
      when gpio-pch is being built as a module.
      
      This was introduced by commit df9541a6 ("gpio: pch9: Use proper flow
      type handlers") that added
      
      	__irq_set_handler_locked(d->irq, handle_edge_irq);
      
      but handle_edge_irq() was not exported for modules (and inlined
      __irq_set_handler_locked() requires irq_to_desc() exported as well)
      Signed-off-by: NJiri Kosina <jkosina@suse.cz>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      3911ff30
  18. 05 5月, 2012 1 次提交
    • T
      genirq: Allow check_wakeup_irqs to notice level-triggered interrupts · d4dc0f90
      Thomas Gleixner 提交于
      Level triggered interrupts do not cause IRQS_PENDING to be set when
      they fire while "disabled" as the 'pending' state is always present in
      the level - they automatically refire where re-enabled.
      
      However the IRQS_PENDING flag is also used to abort a suspend cycle -
      if any 'is_wakeup_set' interrupt is PENDING, check_wakeup_irqs() will
      cause suspend to abort. Without IRQS_PENDING, suspend won't abort.
      
      Consequently, level-triggered interrupts that fire during the 'noirq'
      phase of suspend do not currently abort suspend.
      
      So set IRQS_PENDING even for level triggered interrupts, and make sure
      to clear the flag in check_irq_resend.
      
      [ Changelog by courtesy of Neil ]
      Tested-by: NNeilBrown <neilb@suse.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      d4dc0f90
  19. 06 3月, 2012 1 次提交
    • R
      genirq: Fix long-term regression in genirq irq_set_irq_type() handling · a09b659c
      Russell King 提交于
      In 2008, commit 0c5d1eb7 ("genirq: record trigger type") modified the
      way set_irq_type() handles the 'no trigger' condition.  However, this has
      an adverse effect on PCMCIA support on Intel StrongARM and probably PXA
      platforms.
      
      PCMCIA has several status signals on the socket which can trigger
      interrupts; some of these status signals depend on the card's mode
      (whether it is configured in memory or IO mode).  For example, cards have
      a 'Ready/IRQ' signal: in memory mode, this provides an indication to
      PCMCIA that the card has finished its power up initialization.  In IO
      mode, it provides the device interrupt signal.  Other status signals
      switch between on-board battery status and loud speaker output.
      
      In classical PCMCIA implementations, where you have a specific socket
      controller, the controller provides a method to mask interrupts from the
      socket, and importantly ignore any state transitions on the pins which
      correspond with interrupts once masked.  This masking prevents unwanted
      events caused by the removal and application of socket power being
      forwarded.
      
      However, on platforms where there is no socket controller, the PCMCIA
      status and interrupt signals are routed to standard edge-triggered GPIOs. 
      These GPIOs can be configured to interrupt on rising edge, falling edge,
      or never.  This is where the problems start.
      
      Edge triggered interrupts are required to record events while disabled via
      the usual methods of {free,request,disable,enable}_irq() to prevent
      problems with dropped interrupts (eg, the 8390 driver uses disable_irq()
      to defer the delivery of interrupts).  As a result, these interfaces can
      not be used to implement the desired behaviour.
      
      The side effect of this is that if the 'Ready/IRQ' GPIO is disabled via
      disable_irq() on suspend, and enabled via enable_irq() after resume, we
      will record the state transitions caused by powering events as valid
      interrupts, and foward them to the card driver, which may attempt to
      access a card which is not powered up.
      
      This leads delays resume while drivers spin in their interrupt handlers,
      and complaints from drivers before they realize what's happened.
      
      Moreover, in the case of the 'Ready/IRQ' signal, this is requested and
      freed by the card driver itself; the PCMCIA core has no idea whether the
      interrupt is requested, and, therefore, whether a call to disable_irq()
      would be valid.  (We tried this around 2.4.17 / 2.5.1 kernel era, and
      ended up throwing it out because of this problem.)
      
      Therefore, it was decided back in around 2002 to disable the edge
      triggering instead, resulting in all state transitions on the GPIO being
      ignored.  That's what we actually need the hardware to do.
      
      The commit above changes this behaviour; it explicitly prevents the 'no
      trigger' state being selected.
      
      The reason that request_irq() does not accept the 'no trigger' state is
      for compatibility with existing drivers which do not provide their desired
      triggering configuration.  The set_irq_type() function is 'new' and not
      used by non-trigger aware drivers.
      
      Therefore, revert this change, and restore previously working platforms
      back to their former state.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Cc: linux@arm.linux.org.uk
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: stable@vger.kernel.org
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      a09b659c
  20. 15 2月, 2012 2 次提交
    • T
      genirq: Handle pending irqs in irq_startup() · b4bc724e
      Thomas Gleixner 提交于
      An interrupt might be pending when irq_startup() is called, but the
      startup code does not invoke the resend logic. In some cases this
      prevents the device from issuing another interrupt which renders the
      device non functional.
      
      Call the resend function in irq_startup() to keep things going.
      Reported-and-tested-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Cc: stable@vger.kernel.org
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      b4bc724e
    • T
      genirq: Unmask oneshot irqs when thread was not woken · ac563761
      Thomas Gleixner 提交于
      When the primary handler of an interrupt which is marked IRQ_ONESHOT
      returns IRQ_HANDLED or IRQ_NONE, then the interrupt thread is not
      woken and the unmask logic of the interrupt line is never
      invoked. This keeps the interrupt masked forever.
      
      This was not noticed as most IRQ_ONESHOT users wake the thread
      unconditionally (usually because they cannot access the underlying
      device from hard interrupt context). Though this behaviour was nowhere
      documented and not necessarily intentional. Some drivers can avoid the
      thread wakeup in certain cases and run into the situation where the
      interrupt line s kept masked.
      
      Handle it gracefully.
      Reported-and-tested-by: NLothar Wassmann <lw@karo-electronics.de>
      Cc: stable@vger.kernel.org
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      ac563761
  21. 03 2月, 2012 1 次提交
  22. 03 10月, 2011 1 次提交
    • M
      genirq: Add support for per-cpu dev_id interrupts · 31d9d9b6
      Marc Zyngier 提交于
      The ARM GIC interrupt controller offers per CPU interrupts (PPIs),
      which are usually used to connect local timers to each core. Each CPU
      has its own private interface to the GIC, and only sees the PPIs that
      are directly connect to it.
      
      While these timers are separate devices and have a separate interrupt
      line to a core, they all use the same IRQ number.
      
      For these devices, request_irq() is not the right API as it assumes
      that an IRQ number is visible by a number of CPUs (through the
      affinity setting), but makes it very awkward to express that an IRQ
      number can be handled by all CPUs, and yet be a different interrupt
      line on each CPU, requiring a different dev_id cookie to be passed
      back to the handler.
      
      The *_percpu_irq() functions is designed to overcome these
      limitations, by providing a per-cpu dev_id vector:
      
      int request_percpu_irq(unsigned int irq, irq_handler_t handler,
      		   const char *devname, void __percpu *percpu_dev_id);
      void free_percpu_irq(unsigned int, void __percpu *);
      int setup_percpu_irq(unsigned int irq, struct irqaction *new);
      void remove_percpu_irq(unsigned int irq, struct irqaction *act);
      void enable_percpu_irq(unsigned int irq);
      void disable_percpu_irq(unsigned int irq);
      
      The API has a number of limitations:
      - no interrupt sharing
      - no threading
      - common handler across all the CPUs
      
      Once the interrupt is requested using setup_percpu_irq() or
      request_percpu_irq(), it must be enabled by each core that wishes its
      local interrupt to be delivered.
      
      Based on an initial patch by Thomas Gleixner.
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Link: http://lkml.kernel.org/r/1316793788-14500-2-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      31d9d9b6
  23. 12 9月, 2011 1 次提交
  24. 18 5月, 2011 1 次提交
  25. 23 4月, 2011 1 次提交
  26. 31 3月, 2011 1 次提交
  27. 30 3月, 2011 2 次提交
  28. 29 3月, 2011 2 次提交
  29. 28 3月, 2011 2 次提交
  30. 27 3月, 2011 1 次提交