1. 24 4月, 2009 1 次提交
    • P
      OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files · f248076c
      Paul Walmsley 提交于
      Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
      to use in .init_irq functions to configure the system tick GPTIMER.
      Practical choices at this point are GPTIMER1 or GPTIMER12.  Both of
      these timers are in the WKUP powerdomain, and so are unaffected by
      chip power management.  GPTIMER1 can use sys_clk as a source, for
      applications where a high-resolution timer is more important than
      power management.  GPTIMER12 has the special property that it has the
      secure 32kHz oscillator as its source clock, which may be less prone
      to glitches than the off-chip 32kHz oscillator.  But on HS devices, it
      may not be available for Linux use.
      
      It appears that most boards are fine with GPTIMER1, but BeagleBoard
      should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
      in revisions B4 and below.  Modify board-omap3beagle.c to use GPTIMER12.
      
      This patch originally used a Kbuild config option to select the GPTIMER,
      but was changed to allow this to be specified in board-*.c files, per
      Tony's request.
      
      Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
      this patch - thanks Kalle.
      
      Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
      3430SDP.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      Cc: Kalle Valo <kalle.valo@nokia.com>
      f248076c
  2. 20 2月, 2009 1 次提交
    • R
      [ARM] omap: add support for bypassing DPLLs · c0bf3132
      Russell King 提交于
      This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
      88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
      
      For both OMAP2 and OMAP3, we note the reference and bypass clocks in
      the DPLL data structure.  Whenever we modify the DPLL rate, we first
      ensure that both the reference and bypass clocks are enabled.  Then,
      we decide whether to use the reference and DPLL, or the bypass clock
      if the desired rate is identical to the bypass rate, and program the
      DPLL appropriately.  Finally, we update the clock's parent, and then
      disable the unused clocks.
      
      This keeps the parents correctly balanced, and more importantly ensures
      that the bypass clock is running whenever we reprogram the DPLL.  This
      is especially important because the procedure for reprogramming the DPLL
      involves switching to the bypass clock.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c0bf3132
  3. 14 2月, 2009 1 次提交
    • R
      [ARM] omap: arrange for clock recalc methods to return the rate · 8b9dbc16
      Russell King 提交于
      linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce
      introduces a way to "dry run" clock changes before they're committed.
      However, this involves putting logic to handle this into each and
      every recalc function, and unfortunately due to the caching, led to
      some bugs.
      
      Solve both of issues by making the recalc methods always return the
      clock rate for the clock, which the caller decides what to do with.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      8b9dbc16
  4. 09 2月, 2009 5 次提交
  5. 08 2月, 2009 5 次提交
  6. 02 2月, 2009 2 次提交
  7. 11 12月, 2008 1 次提交
    • T
      omap mmc: Add better MMC low-level init · d8874665
      Tony Lindgren 提交于
      This will simplify the MMC low-level init, and make it more
      flexible to add support for a newer MMC controller in the
      following patches.
      
      The patch rearranges platform data and gets rid of slot vs
      controller confusion in the old data structures. Also fix
      device id numbering in the clock code.
      
      Some code snippets are based on an earlier patch by
      Russell King <linux@arm.linux.org.uk>.
      
      Cc: Pierre Ossman <drzeus-mmc@drzeus.cx>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      
      
      
      
      
      d8874665
  8. 22 11月, 2008 1 次提交
  9. 19 8月, 2008 1 次提交
  10. 03 7月, 2008 2 次提交
    • P
      ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm · 88b8ba90
      Paul Walmsley 提交于
      This patch adds a new rate rounding algorithm for DPLL clocks on the
      OMAP2/3 architecture.
      
      For a desired DPLL target rate, there may be several
      multiplier/divider (M, N) values which will generate a sufficiently
      close rate.  Lower N values result in greater power economy.  However,
      lower N values can cause the difference between the rounded rate and
      the target rate ("rate error") to be larger than it would be with a
      higher N.  This can cause downstream devices to run more slowly than
      they otherwise would.
      
      This DPLL rate rounding algorithm:
      
      - attempts to find the lowest possible N (DPLL divider) to reach the
        target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
        lower N values save more power than higher N values).
      
      - allows developers to set an upper bound on the error between the
        rounded rate and the desired target rate ("rate tolerance"), so an
        appropriate balance between rate fidelity and power savings can be
        set.  This maximum rate error tolerance is set via
        omap2_set_dpll_rate_tolerance().
      
      - never returns a rounded rate higher than the target rate.
      
      The rate rounding algorithm caches the last rounded M, N, and rate
      computation to avoid rounding the rate twice for each clk_set_rate()
      call.  (This patch does not yet implement set_rate for DPLLs; that
      follows in a future patch.)
      
      The algorithm trades execution speed for rate accuracy.  It will find
      the (M, N) set that results in the least rate error, within a
      specified rate tolerance.  It does this by evaluating each divider
      setting - on OMAP3, this involves 128 steps.  Another approach to DPLL
      rate rounding would be to bail out as soon as a valid rate is found
      within the rate tolerance, which would trade rate accuracy for
      execution speed.  Alternate implementations welcome.
      
      This code is not yet used by the OMAP24XX DPLL clock, since it
      is currently defined as a composite clock, fusing the DPLL M,N and the
      M2 output divider.  This patch also renames the existing OMAP24xx DPLL
      programming functions to highlight that they program both the DPLL and
      the DPLL's output multiplier.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      88b8ba90
    • E
      ARM: OMAP: McBSP: Add support for mcbsp on mach-omap1 · 44ec9a33
      Eduardo Valentin 提交于
      This patch adds support for mach-omap1 based on current
      mcbsp platform driver.
      Signed-off-by: NEduardo Valentin <eduardo.valentin@indt.org.br>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      44ec9a33
  11. 15 4月, 2008 4 次提交
  12. 21 5月, 2007 1 次提交
  13. 07 3月, 2007 1 次提交
  14. 25 9月, 2006 2 次提交
  15. 27 6月, 2006 1 次提交
  16. 03 4月, 2006 1 次提交
  17. 18 1月, 2006 1 次提交
  18. 10 11月, 2005 1 次提交