Add support for DEBUG_LL on the 8660 and 8960 development boards.
While we're here cleanup the uncompress.h code a bit. Avoid
the use of readl/writel as those are Linux specific APIs that
aren't guaranteed to work in the decompressor.

Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Now that DEBUG_LL is a choice we can move MSM's homegrown choice
menu to DEBUG_LL.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

This allows boards with non-standard sdio cards to fill the CIS/CCCR data.
It is particularly important for old msm72k boards using wl1251.
Also drop the obsolete embedded_sdio_data structure from the header
as it was intended to surve a similiar purpose but was not implemented.
Signed-off-by: NAlexander Tarasikov <alexander.tarasikov@gmail.com>
Acked-by: NSahitya Tummala <stummala@codeaurora.org>
[davidb: minor formatting cleanup]
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).

Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.

This also allows the removal of some duplicated code.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Tested-by: NDavid Brown <davidb@codeaurora.org>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Some platforms (like OMAP not to name it) are doing rather complicated
hacks just to determine the base UART address to use.  Let's give their
addruart macro some slack by providing an extra work register which will
allow for much needed cleanups.

This is basically a no-op as this commit is only adding the extra argument
to the macro but no one is using it yet.
Signed-off-by: Nnicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: NKevin Hilman <khilman@ti.com>

MSMs post 8x50 have 2Mb at the beginning of RAM reserved for
shared memory. Since the kernel hasn't typically been told this
RAM exists, PHYS_OFFSET has been set to 0xN0200000 and the memory
atags passed to the kernel have matched. This doesn't play nicely
with things such as AUTO_ZRELADDR, which doesn't work at all, and
dynamic phys to virt, which requires an MSM specific workaround.

Work around these issues by telling the kernel RAM starts at
0xN0000000 (it actually does) and fixup the atags from the
bootloader (if necessary) to say the same. In addition, make sure
to set TEXT_OFFSET at least 2Mb beyond the start of RAM so that
the kernel doesn't end up being decompressed into shared memory.

After doing this, AUTO_ZRELADDR should work on MSM with no
problems and ARM_PATCH_PHYS_VIRT_16BIT should no longer be
necessary.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than marking the mach/gpio.h header files which want to use the
trivial GPIOLIB implementation, mark those which do not want to use it
instead.  This means that by default, you get the trivial implementation
and only have to do something extra if you need to.  This should
encourage the use of the trivial default implementation.

As an additional bonus, several gpio.h header files become empty.
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: NJamie Iles <jamie@jamieiles.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Many of the gpio_to_irq implementations use the gpiolib version of this
function.  Provide the standard gpiolib gpio_to_irq() for everyone, but
allow platforms to override it if they wish.  Add the neccessary
overrides for those platforms which do not use the standard definition.
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Consolidate 24 trivial gpiolib implementions out of mach/gpio.h
into asm/gpio.h.  This is basically the include of asm-generic/gpio.h
and the definition of gpio_get_value, gpio_set_value, and gpio_cansleep
as described in Documentation/gpio.txt
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Tested-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The gpiomux.h header contains some SOC ifdefs.  However, the API that
is actually used by the GPIO driver only uses two functions that are
general.  Move these general definitions into a public header file.

Change-Id: Ia5df8af87dba268225598d56908e523bcfc24ef6
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>

The two GPIO controllers are always mapped to the same virtual address
across all MSM devices.  Instead of selecting this at compile time,
determine the physical address at runtime, eliminating yet something
else preventing multiple MSM targets from being compiled into the same
kernel.

Change-Id: I1672219d978ab6243526adeda6badf49472baa27
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Now most of ARM machines has the alsmot same __clk_get/put() macro

So place it at the arch/arm/include/asm/clkdev.h and remove the reduntant header files

But some machines don't have the same form as above. It can use the machince specific clkdev file by HAVE_MACH_CLKDEV config

Now there are only 3 caese.

1) define the clk structure with clkdev macro => Need to move clk structure to proper header file

arch/arm/mach-versatile/include/mach/clkdev.h
arch/arm/mach-realview/include/mach/clkdev.h
arch/arm/mach-vexpress/include/mach/clkdev.h
arch/arm/mach-integrator/include/mach/clkdev.h

2) export the __clk_get/put function at clock.c

arch/arm/mach-shmobile/include/mach/clkdev.h

3) demuxing the clk source
arch/arm/mach-u300/include/mach/clkdev.h
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

Rather than having each platform class provide a mach/smp.h header for
smp_cross_call(), arrange for them to register the function with the
core ARM SMP code instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

- kenrel -> kernel
- whetehr -> whether
- ttt -> tt
- sss -> ss
Signed-off-by: NJustin P. Mattock <justinmattock@gmail.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Don't read from V2Pxx command registers when doing
iova-to-phys operations. These registers are write-only and
reading the value before modifying the VA bits is
unnecessary.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Remove the depencency on the IOMMU IDR register, as it may
not be accessible depending on the security configuraton.
This involves moving the NCB field of IDR into the platform
data.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Use ASID tags in the TLB instead of VMID tags in
preparation for changes to the secure environment.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Clean up the clock control code in the probe calls, and add
support for controlling the clock for the IOMMU bus
interconnect. With the (proper) clock driver in place, the
clock control logic in the probe function can be made much
cleaner since it does not have to deal with the placeholder
driver anymore.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Reviewed-by: NTrilok Soni <tsoni@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add clock control to the IOMMU driver. The IOMMU bus clock
(and potentially an AXI clock) need to be on to gain access
to IOMMU registers. Actively control these clocks when
needed instead of leaving them on.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Migrating to clkdev has several advantages:

 * Less code in mach-msm/clock.c

 * A more robust clk_get() implementation

 * clk_add_alias() support

 * clk_get_sys() support

In general, this will help board authors setup clock aliases and
break the dependency on device pointers in the clock tables.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Replace a BSD-style license in Code Aurora Forum authored files with
an explicit GPLv2.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

This uncouple PHYS_OFFSET from the platform definitions, thereby
facilitating run-time computation of the physical memory offset.
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NWan ZongShun <mcuos.com@gmail.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Acked-by: NJiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Make the IOMMU platform data target-independent in
preparation for adding MSM8960 IOMMU support. The IOMMU
configuration on MSM8x60 and MSM8960 is identical and the
same platform data can be used for both.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Remove ifdefs that do nothing, either from having the code
between them previously removed, or from having been
accidentally added to the wrong file.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>

Configure SDCC GPIOs when the host is powered up or powered off.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>

Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add the interrupt map for the Qualcomm MSM8960 chip. This
chip has an interrupt map that is different from previous
targets.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add the physical memory offset value for the Qualcomm
MSM8960 chip.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add the register address definitions for the basic hardware
blocks on the Qualcomm MSM8960 chip.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

The QGIC registers are mapped to the same virtual addresses across
targets, only the physical address changes.  Move the BASE address out
of target-specific files, and add a SOC name to the base addresses.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Allow the timer register to be determined dynamically instead of at
compile time.  Use common virtual addresses for the registers across
all MSM chips, and select the register mappings based on the detected
CPU.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Create runtime queries to distinguish the various MSM targets.
Although these would probably be better named soc_is..., use
cpu_is... to match convention in the rest of the kernel.

Hard code the tests based on config options for now.  When runtime
device detection is implemented, these can be made dynamic.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

The msm provides timer hardware that is private to each core. Each
timer has separate counter and match registers, so we create separate
clock_event_devices for each core. For the global clocksource, use
cpu 0's counter.
Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add USB OTG, peripheral and host devices.  This patch also adds
usb_phy_clk which is required for resetting the PHY.  VBUS power up
and shutdown routines depends on PMIC module.  As PMIC driver is
unavailable, configure USB in peripheral only mode.
Signed-off-by: NPavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI.  Recover the SGI number via do_IPI.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add the register field definitions and memory attribute
definitions that will be needed to support IOMMU
transactions with cache-coherent memory access.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add register addresses and IRQ numbers for the IOMMU used
for the second 2D graphics core.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>