1. 27 6月, 2016 1 次提交
  2. 08 1月, 2016 4 次提交
  3. 17 11月, 2015 1 次提交
    • P
      net: smsc911x: Reset PHY during initialization · cd998ecd
      Pavel Fedin 提交于
      On certain hardware after software reboot the chip may get stuck and fail
      to reinitialize during reset. This can be fixed by ensuring that PHY is
      reset too.
      
      Old PHY resetting method required operational MDIO interface, therefore
      the chip should have been already set up. In order to be able to function
      during probe, it is changed to use PMT_CTRL register.
      
      The problem could be observed on SMDK5410 board.
      Signed-off-by: NPavel Fedin <p.fedin@samsung.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      cd998ecd
  4. 02 11月, 2015 1 次提交
    • P
      net: smsc911x: Fix crash if loopback test fails · b43c142f
      Pavel Fedin 提交于
      On certain hardware in certain situations loopback test fails and the
      driver gets removed. During mdiobus_unregister() instance of PHY driver
      gets disposed. But by this time it has already been started using
      phy_connect_direct().
      
      PHY driver uses DELAYED_WORK in order to maintain its state. Attempting
      to dispose the driver without calling phy_disconnect() causes deallocation
      of DELAYED_WORK being active. This shortly causes a bad crash in timer
      code.
      
      The problem can be discovered by enabling CONFIG_DEBUG_OBJECTS_TIMERS and
      CONFIG_DEBUG_OBJECTS_FREE
      Signed-off-by: NPavel Fedin <p.fedin@samsung.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b43c142f
  5. 30 8月, 2015 1 次提交
  6. 28 8月, 2015 1 次提交
  7. 21 8月, 2015 1 次提交
  8. 18 8月, 2015 1 次提交
    • G
      smsc911x: Fix crash seen if neither ACPI nor OF is configured or used · 62ee783b
      Guenter Roeck 提交于
      Commit 0b50dc4f ("Convert smsc911x to use ACPI as well as DT") makes
      the call to smsc911x_probe_config() unconditional, and no longer fails if
      there is no device node. device_get_phy_mode() is called unconditionally,
      and if there is no phy node configured returns an error code. This error
      code is assigned to phy_interface, and interpreted elsewhere in the code
      as valid phy mode. This in turn causes qemu to crash when running a
      variant of realview_pb_defconfig.
      
      	qemu: hardware error: lan9118_read: Bad reg 0x86
      
      Fixes: 0b50dc4f ("Convert smsc911x to use ACPI as well as DT")
      Cc: Jeremy Linton <jeremy.linton@arm.com>
      Cc Graeme Gregory <graeme.gregory@linaro.org>
      Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      62ee783b
  9. 14 8月, 2015 1 次提交
  10. 05 5月, 2015 1 次提交
    • K
      net/smsc911x: fix irq resource allocation failure · 965b2aa7
      Kamlakant Patel 提交于
      When smsc911x uses GPIO as the interrupt controller, and if both are
      loaded as modules, we get following error:
      
      "smsc911x: Could not allocate irq resource"
      
      This issue is because of smsc911x using platform_get_resource to get
      device tree based irq resource.
      
      commit "9ec36caf (of/irq: do irq resolution in platform_get_irq)" and
      commit "7085a7 (drivers: platform: parse IRQ flags from resources)" add
      support in platform_get_irq to resolve irq and irq_flags respectively
      for both modern device tree and legacy static platform data platforms.
      
      Modify smsc911x driver to use platform_get_irq to pick up irq resource
      correctly and use irq_get_trigger_type to get the IRQ trigger flags.
      Signed-off-by: NKamlakant Patel <kamlakant.patel@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      965b2aa7
  11. 04 3月, 2015 1 次提交
  12. 25 11月, 2014 1 次提交
    • G
      net/smsc911x: Add minimal runtime PM support · 3a611e26
      Geert Uytterhoeven 提交于
      Add minimal runtime PM support (enable on probe, disable on remove), to
      ensure proper operation with a parent device that uses runtime PM.
      
      This is needed on systems where the external bus controller module of
      the SoC is contained in a PM domain and/or has a gateable functional
      clock. In such cases, before accessing any device connected to the
      external bus, the PM domain must be powered up, and/or the functional
      clock must be enabled, which is typically handled through runtime PM by
      the bus controller driver.
      
      An example of this is the kzm9g development board, where an smsc9220
      Ethernet controller is connected to the Bus State Controller (BSC) of a
      Renesas sh73a0 SoC.
      Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3a611e26
  13. 14 11月, 2014 3 次提交
    • E
      smsc911x: power-up phydev before doing a software reset. · ccf899a2
      Enric Balletbo i Serra 提交于
      With commit be9dad1f ("net: phy: suspend phydev when going
      to HALTED"), the PHY device will be put in a low-power mode using
      BMCR_PDOWN if the the interface is set down. The smsc911x driver does
      a software_reset opening the device driver (ndo_open). In such case,
      the PHY must be powered-up before access to any register and before
      calling the software_reset function. Otherwise, as the PHY is powered
      down the software reset fails and the interface can not be enabled
      again.
      
      This patch fixes this scenario that is easy to reproduce setting down
      the network interface and setting up again.
      
          $ ifconfig eth0 down
          $ ifconfig eth0 up
          ifconfig: SIOCSIFFLAGS: Input/output error
      Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ccf899a2
    • A
      net/smsc911x: Fix delays in the PHY enable/disable routines · 6ff53fd3
      Alexander Kochetkov 提交于
      Increased delay in the smsc911x_phy_disable_energy_detect (from 1ms to 2ms).
      Dropped delays in the smsc911x_phy_enable_energy_detect (100ms and 1ms).
      
      The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221).
      
      I saw problems with soft reset due to wrong udelay timings.
      After I fixed udelay, I measured the time needed to bring integrated PHY
      from power-down to operational mode (the time beetween clearing EDPWRDOWN
      bit and soft reset complete event). I got 1ms (measured using ktime_get).
      The value is equal to the current value (1ms) used in the
      smsc911x_phy_disable_energy_detect. It is near the upper bound and in order
      to avoid rare soft reset faults it is doubled (2ms).
      
      I don't know official timing for bringing up integrated PHY as specs doesn't
      clarify this (or may be I didn't found).
      
      It looks safe to drop delays before and after setting EDPWRDOWN bit
      (enable PHY power-down mode). I didn't saw any regressions with the patch.
      
      The patch was reviewed by Steve Glendinning and Microchip Team.
      Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
      Acked-by: NSteve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6ff53fd3
    • A
      net/smsc911x: Fix rare soft reset timeout issue due to PHY power-down mode · 242bcd5b
      Alexander Kochetkov 提交于
      The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221).
      
      It is possible that PHY could enter power-down mode (ENERGYON clear),
      between ENERGYON bit check in smsc911x_phy_disable_energy_detect and SRST
      bit set in smsc911x_soft_reset. This could happen, for example, if someone
      disconnect ethernet cable between the checks. The PHY in a power-down mode
      would prevent the MAC portion of chip to be software reseted.
      
      Initially found by code review, confirmed later using test case.
      
      This is low probability issue, and in order to reproduce it you have to
      run the script:
      
      while true; do
      	ifconfig eth0 down
      	ifconfig eth0 up || break
      done
      
      While the script is running you have to plug/unplug ethernet cable many
      times (using gpio controlled ethernet switch, for example) until get:
      
      [ 4516.477783] ADDRCONF(NETDEV_UP): eth0: link is not ready
      [ 4516.512207] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 0xce006000, IRQ: 336
      [ 4516.524658] ADDRCONF(NETDEV_UP): eth0: link is not ready
      [ 4516.559082] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 0xce006000, IRQ: 336
      [ 4516.571990] ADDRCONF(NETDEV_UP): eth0: link is not ready
      ifconfig: SIOCSIFFLAGS: Input/output error
      
      The patch was reviewed by Steve Glendinning and Microchip Team.
      Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
      Acked-by: NSteve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      242bcd5b
  14. 20 10月, 2014 1 次提交
  15. 04 10月, 2014 1 次提交
  16. 04 6月, 2014 1 次提交
  17. 27 3月, 2014 2 次提交
  18. 25 3月, 2014 1 次提交
  19. 21 3月, 2014 1 次提交
  20. 07 12月, 2013 1 次提交
    • J
      ethernet: Fix FSF address in file headers · 0ab75ae8
      Jeff Kirsher 提交于
      Several files refer to an old address for the Free Software Foundation
      in the file header comment.  Resolve by replacing the address with
      the URL <http://www.gnu.org/licenses/> so that we do not have to keep
      updating the header comments anytime the address changes.
      
      CC: Santosh Raspatur <santosh@chelsio.com>
      CC: Dimitris Michailidis <dm@chelsio.com>
      CC: Michael Chan <mchan@broadcom.com>
      CC: Santiago Leon <santil@linux.vnet.ibm.com>
      CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      CC: Olof Johansson <olof@lixom.net>
      CC: Manish Chopra <manish.chopra@qlogic.com>
      CC: Sony Chacko <sony.chacko@qlogic.com>
      CC: Rajesh Borundia <rajesh.borundia@qlogic.com>
      CC: Nicolas Pitre <nico@fluxnic.net>
      CC: Steve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0ab75ae8
  21. 02 11月, 2013 1 次提交
  22. 03 10月, 2013 1 次提交
  23. 31 8月, 2013 1 次提交
  24. 28 5月, 2013 1 次提交
  25. 19 3月, 2013 1 次提交
  26. 02 3月, 2013 1 次提交
  27. 15 1月, 2013 1 次提交
  28. 04 1月, 2013 1 次提交
  29. 20 12月, 2012 1 次提交
  30. 12 12月, 2012 1 次提交
  31. 08 12月, 2012 1 次提交
  32. 04 12月, 2012 1 次提交
  33. 20 11月, 2012 1 次提交
  34. 15 11月, 2012 1 次提交
    • K
      net/smsc911x: Fix ready check in cases where WORD_SWAP is needed · 769ce4c9
      Kamlakant Patel 提交于
      The chip ready check added by the commit 3ac3546e [Always wait for
      the chip to be ready] does not work when the register read/write
      is word swapped. This check has been added before the WORD_SWAP
      register is programmed, so we need to check for swapped register
      value as well.
      
      Bit 16 is marked as RESERVED in SMSC datasheet, Steve Glendinning
      <steve@shawell.net> checked with SMSC and wrote:
      
        The chip architects have concluded we should be reading PMT_CTRL
        until we see any of bits 0, 8, 16 or 24 set.  Then we should read
        BYTE_TEST to check the byte order is correct (as we already do).
      
        The rationale behind this is that some of the chip variants have
        word order swapping features too, so the READY bit could actually
        be in any of the 4 possible locations.  The architects have confirmed
        that if any of these 4 positions is set the chip is ready.  The other
        3 locations will either never be set or can only go high after READY
        does (so also indicate the device is ready).
      
      This change will check for the READY bit at the 16th position. We do
      not check the other two cases (bit 8 and 24) since the driver does not
      support byte-swapped register read/write.
      Signed-off-by: NKamlakant Patel <kamlakant.patel@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      769ce4c9