1. 15 4月, 2014 1 次提交
  2. 14 2月, 2014 3 次提交
  3. 04 2月, 2014 3 次提交
  4. 04 1月, 2014 4 次提交
  5. 21 12月, 2013 2 次提交
  6. 20 12月, 2013 1 次提交
  7. 13 12月, 2013 1 次提交
  8. 15 11月, 2013 1 次提交
  9. 07 11月, 2013 1 次提交
    • K
      PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq() · 0e4ccb15
      Konrad Rzeszutek Wilk 提交于
      Certain platforms do not allow writes in the MSI-X BARs to setup or tear
      down vector values.  To combat against the generic code trying to write to
      that and either silently being ignored or crashing due to the pagetables
      being marked R/O this patch introduces a platform override.
      
      Note that we keep two separate, non-weak, functions default_mask_msi_irqs()
      and default_mask_msix_irqs() for the behavior of the arch_mask_msi_irqs()
      and arch_mask_msix_irqs(), as the default behavior is needed by x86 PCI
      code.
      
      For Xen, which does not allow the guest to write to MSI-X tables - as the
      hypervisor is solely responsible for setting the vector values - we
      implement two nops.
      
      This fixes a Xen guest crash when passing a PCI device with MSI-X to the
      guest.  See the bugzilla for more details.
      
      [bhelgaas: add bugzilla info]
      Reference: https://bugzilla.kernel.org/show_bug.cgi?id=64581Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      CC: Sucheta Chakraborty <sucheta.chakraborty@qlogic.com>
      CC: Zhenzhong Duan <zhenzhong.duan@oracle.com>
      0e4ccb15
  10. 30 10月, 2013 1 次提交
  11. 13 9月, 2013 1 次提交
  12. 13 8月, 2013 1 次提交
  13. 12 8月, 2013 2 次提交
  14. 29 5月, 2013 1 次提交
    • A
      PCI: Allocate only as many MSI vectors as requested by driver · 65f6ae66
      Alexander Gordeev 提交于
      Because of the encoding of the "Multiple Message Capable" and "Multiple
      Message Enable" fields, a device can only advertise that it's capable of a
      power-of-two number of vectors, and the OS can only enable a power-of-two
      number.
      
      For example, a device that's limited internally to using 18 vectors would
      have to advertise that it's capable of 32.  The 14 extra vectors consume
      vector numbers and IRQ descriptors even though the device can't actually
      use them.
      
      This fix introduces a 'msi_desc::nvec_used' field to address this issue.
      When non-zero, it is the actual number of MSIs the device will send, as
      requested by the device driver.  This value should be used by architectures
      to set up and tear down only as many interrupt resources as the device will
      actually use.
      
      Note, although the existing 'msi_desc::multiple' field might seem
      redundant, in fact it is not.  The number of MSIs advertised need not be
      the smallest power-of-two larger than the number of MSIs the device will
      send.  Thus, it is not always possible to derive the former from the
      latter, so we need to keep them both to handle this case.
      
      [bhelgaas: changelog, rename to "nvec_used"]
      Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      65f6ae66
  15. 30 4月, 2013 1 次提交
  16. 23 4月, 2013 13 次提交
  17. 13 4月, 2013 1 次提交
  18. 25 1月, 2013 1 次提交
  19. 01 12月, 2012 1 次提交
    • J
      s390/pci: PCI adapter interrupts for MSI/MSI-X · 9a4da8a5
      Jan Glauber 提交于
      Support PCI adapter interrupts using the Single-IRQ-mode. Single-IRQ-mode
      disables an adapter IRQ automatically after delivering it until the SIC
      instruction enables it again. This is used to reduce the number of IRQs
      for streaming workloads.
      
      Up to 64 MSI handlers can be registered per PCI function.
      A hash table is used to map interrupt numbers to MSI descriptors.
      The interrupt vector is scanned using the flogr instruction.
      Only MSI/MSI-X interrupts are supported, no legacy INTs.
      Signed-off-by: NJan Glauber <jang@linux.vnet.ibm.com>
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      9a4da8a5