1. 13 2月, 2007 1 次提交
  2. 01 7月, 2006 1 次提交
  3. 10 2月, 2006 2 次提交
  4. 14 11月, 2005 1 次提交
  5. 20 10月, 2005 1 次提交
  6. 01 10月, 2005 1 次提交
  7. 19 9月, 2005 1 次提交
  8. 10 9月, 2005 1 次提交
  9. 05 9月, 2005 1 次提交
    • K
      [PATCH] ppc32: Added support for the Book-E style Watchdog Timer · a2f40ccd
      Kumar Gala 提交于
      PowerPC 40x and Book-E processors support a watchdog timer at the processor
      core level.  The timer has implementation dependent timeout frequencies
      that can be configured by software.
      
      One the first Watchdog timeout we get a critical exception.  It is left to
      board specific code to determine what should happen at this point.  If
      nothing is done and another timeout period expires the processor may
      attempt to reset the machine.
      
      Command line parameters:
        wdt=0 : disable watchdog (default)
        wdt=1 : enable watchdog
      
        wdt_period=N : N sets the value of the Watchdog Timer Period.
      
        The Watchdog Timer Period meaning is implementation specific. Check
        User Manual for the processor for more details.
      
      This patch is based off of work done by Takeharu Kato.
      Signed-off-by: NMatt McClintock <msm@freescale.com>
      Signed-off-by: NKumar Gala <kumar.gala@freescale.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      a2f40ccd
  10. 26 6月, 2005 1 次提交
  11. 29 5月, 2005 1 次提交
  12. 01 5月, 2005 1 次提交
  13. 17 4月, 2005 2 次提交
    • K
      [PATCH] ppc32: Support 36-bit physical addressing on e500 · f50b153b
      Kumar Gala 提交于
      To add support for 36-bit physical addressing on e500 the following changes
      have been made.  The changes are generalized to support any physical address
      size larger than 32-bits:
      
      * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits
        of flags.
      
      * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of
        updating hardware register (SPRN_MAS7) which holds the upper 32-bits of
        physical address that will be written into the TLB.  This is useful since
        not all e500 cores support 36-bit physical addressing.
      
      * Currently have a pass through implementation of fixup_bigphys_addr
      
      * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional
        storage attributes that may exist in future FSL Book-E cores and updated
        fault handler to copy these bits into the hardware TLBs.
      Signed-off-by: NKumar Gala <kumar.gala@freescale.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f50b153b
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4