1. 01 2月, 2017 1 次提交
  2. 25 1月, 2017 1 次提交
    • C
      drm/i915: Move atomic state free from out of fence release · 6f0f02dc
      Chris Wilson 提交于
      Fences are required to support being released from under an atomic context.
      The drm_atomic_state struct may take a mutex when being released and so
      we cannot drop a reference to the drm_atomic_state from the fence release
      path directly, and so we need to defer that unreference to a worker.
      
      [  326.576697] WARNING: CPU: 2 PID: 366 at kernel/sched/core.c:7737 __might_sleep+0x5d/0x80
      [  326.576816] do not call blocking ops when !TASK_RUNNING; state=1 set at [<ffffffffc0359549>] intel_breadcrumbs_signaler+0x59/0x270 [i915]
      [  326.576818] Modules linked in: rfcomm fuse snd_hda_codec_hdmi bnep snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq snd_seq_device snd_timer input_leds led_class snd punit_atom_debug btusb btrtl btbcm btintel intel_rapl bluetooth i915 drm_kms_helper syscopyarea sysfillrect iwlwifi sysimgblt soundcore fb_sys_fops mei_txe cfg80211 drm pwm_lpss_platform pwm_lpss pinctrl_cherryview fjes acpi_pad parport_pc ppdev parport autofs4
      [  326.576899] CPU: 2 PID: 366 Comm: i915/signal:0 Tainted: G     U          4.10.0-rc3-patser+ #5030
      [  326.576902] Hardware name:                  /NUC5PPYB, BIOS PYBSWCEL.86A.0031.2015.0601.1712 06/01/2015
      [  326.576905] Call Trace:
      [  326.576920]  dump_stack+0x4d/0x6d
      [  326.576926]  __warn+0xc0/0xe0
      [  326.576931]  warn_slowpath_fmt+0x5a/0x80
      [  326.577004]  ? intel_breadcrumbs_signaler+0x59/0x270 [i915]
      [  326.577075]  ? intel_breadcrumbs_signaler+0x59/0x270 [i915]
      [  326.577079]  __might_sleep+0x5d/0x80
      [  326.577087]  mutex_lock+0x1b/0x40
      [  326.577133]  drm_property_free_blob+0x1e/0x80 [drm]
      [  326.577167]  ? drm_property_destroy+0xe0/0xe0 [drm]
      [  326.577200]  drm_mode_object_unreference+0x5c/0x70 [drm]
      [  326.577233]  drm_property_unreference_blob+0xe/0x10 [drm]
      [  326.577260]  __drm_atomic_helper_crtc_destroy_state+0x14/0x40 [drm_kms_helper]
      [  326.577278]  drm_atomic_helper_crtc_destroy_state+0x10/0x20 [drm_kms_helper]
      [  326.577352]  intel_crtc_destroy_state+0x9/0x10 [i915]
      [  326.577388]  drm_atomic_state_default_clear+0xea/0x1d0 [drm]
      [  326.577462]  intel_atomic_state_clear+0xd/0x20 [i915]
      [  326.577497]  drm_atomic_state_clear+0x1a/0x30 [drm]
      [  326.577532]  __drm_atomic_state_free+0x13/0x60 [drm]
      [  326.577607]  intel_atomic_commit_ready+0x6f/0x78 [i915]
      [  326.577670]  i915_sw_fence_release+0x3a/0x50 [i915]
      [  326.577733]  dma_i915_sw_fence_wake+0x39/0x80 [i915]
      [  326.577741]  dma_fence_signal+0xda/0x120
      [  326.577812]  ? intel_breadcrumbs_signaler+0x59/0x270 [i915]
      [  326.577884]  intel_breadcrumbs_signaler+0xb1/0x270 [i915]
      [  326.577889]  kthread+0x127/0x130
      [  326.577961]  ? intel_engine_remove_wait+0x1a0/0x1a0 [i915]
      [  326.577964]  ? kthread_stop+0x120/0x120
      [  326.577970]  ret_from_fork+0x22/0x30
      
      Fixes: c004a90b ("drm/i915: Restore nonblocking awaits for modesetting")
      Reported-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170123212939.30345-1-chris@chris-wilson.co.uk
      Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.10-rc1+
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      (cherry picked from commit eb955eee)
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      6f0f02dc
  3. 17 11月, 2016 2 次提交
  4. 15 11月, 2016 3 次提交
  5. 09 11月, 2016 1 次提交
  6. 01 11月, 2016 13 次提交
  7. 31 10月, 2016 1 次提交
  8. 29 10月, 2016 3 次提交
  9. 28 10月, 2016 1 次提交
  10. 26 10月, 2016 5 次提交
  11. 25 10月, 2016 2 次提交
    • S
      drm/i915: Support for GuC interrupts · 26705e20
      Sagar Arun Kamble 提交于
      There are certain types of interrupts which Host can receive from GuC.
      GuC ukernel sends an interrupt to Host for certain events, like for
      example retrieve/consume the logs generated by ukernel.
      This patch adds support to receive interrupts from GuC but currently
      enables & partially handles only the interrupt sent by GuC ukernel.
      Future patches will add support for handling other interrupt types.
      
      v2:
      - Use common low level routines for PM IER/IIR programming (Chris)
      - Rename interrupt functions to gen9_xxx from gen8_xxx (Chris)
      - Replace disabling of wake ref asserts with rpm get/put (Chris)
      
      v3:
      - Update comments for more clarity. (Tvrtko)
      - Remove the masking of GuC interrupt, which was kept masked till the
        start of bottom half, its not really needed as there is only a
        single instance of work item & wq is ordered. (Tvrtko)
      
      v4:
      - Rebase.
      - Rename guc_events to pm_guc_events so as to be indicative of the
        register/control block it is associated with. (Chris)
      - Add handling for back to back log buffer flush interrupts.
      
      v5:
      - Move the read & clearing of register, containing Guc2Host message
        bits, outside the irq spinlock. (Tvrtko)
      
      v6:
      - Move the log buffer flush interrupt related stuff to the following
        patch so as to do only generic bits in this patch. (Tvrtko)
      - Rebase.
      
      v7:
      - Remove the interrupts_enabled check from gen9_guc_irq_handler, want to
        process that last interrupt also before disabling the interrupt, sync
        against the work queued by irq handler will be done by caller disabling
        the interrupt.
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      26705e20
    • A
      drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set · f4e9af4f
      Akash Goel 提交于
      So far PM IER/IIR/IMR registers were being used only for Turbo related
      interrupts. But interrupts coming from GuC also use the same set.
      As a precursor to supporting GuC interrupts, added new low level routines
      so as to allow sharing the programming of PM IER/IIR/IMR registers between
      Turbo & GuC.
      Also similar to PM IMR, maintaining a bitmask for PM IER register, to allow
      easy sharing of it between Turbo & GuC without involving a rmw operation.
      
      v2:
      - For appropriateness & avoid any ambiguity, rename old functions
        enable/disable pm_irq to mask/unmask pm_irq and rename new functions
        enable/disable pm_interrupts to enable/disable pm_irq. (Tvrtko)
      - Use u32 in place of uint32_t. (Tvrtko)
      
      v3:
      - Rename the fields pm_irq_mask & pm_ier_mask and do some cleanup. (Chris)
      - Rebase.
      
      v4: Fix the inadvertent disabling of User interrupt for VECS ring causing
          failure for certain IGTs.
      
      v5: Use dev_priv with HAS_VEBOX macro. (Tvrtko)
      Suggested-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      f4e9af4f
  12. 24 10月, 2016 1 次提交
  13. 22 10月, 2016 2 次提交
  14. 20 10月, 2016 3 次提交
  15. 18 10月, 2016 1 次提交