1. 16 10月, 2008 2 次提交
  2. 13 10月, 2008 10 次提交
  3. 12 10月, 2008 2 次提交
    • I
      x86: memory corruption check - cleanup · 46eaa670
      Ingo Molnar 提交于
      Move the prototypes from the generic kernel.h header to the more
      appropriate include/asm-x86/bios_ebda.h header file.
      
      Also, remove the check from the power management code - this is a
      pure x86 matter for now.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      46eaa670
    • A
      x86, early_ioremap: fix fencepost error · c613ec1a
      Alan Cox 提交于
      The x86 implementation of early_ioremap has an off by one error. If we get
      an object which ends on the first byte of a page we undermap by one page and
      this causes a crash on boot with the ASUS P5QL whose DMI table happens to fit
      this alignment.
      
      The size computation is currently
      
      	last_addr = phys_addr + size - 1;
      	npages = (PAGE_ALIGN(last_addr) - phys_addr)
      
      (Consider a request for 1 byte at alignment 0...)
      
      Closes #11693
      
      Debugging work by Ian Campbell/Felix Geyer
      Signed-off-by: NAlan Cox <alan@rehat.com>
      Cc: <stable@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c613ec1a
  4. 11 10月, 2008 9 次提交
    • S
      x86, cpa: make the kernel physical mapping initialization a two pass sequence, fix · b27a43c1
      Suresh Siddha 提交于
      Jeremy Fitzhardinge wrote:
      
      > I'd noticed that current tip/master hasn't been booting under Xen, and I
      > just got around to bisecting it down to this change.
      >
      > commit 065ae73c5462d42e9761afb76f2b52965ff45bd6
      > Author: Suresh Siddha <suresh.b.siddha@intel.com>
      >
      >    x86, cpa: make the kernel physical mapping initialization a two pass sequence
      >
      > This patch is causing Xen to fail various pagetable updates because it
      > ends up remapping pagetables to RW, which Xen explicitly prohibits (as
      > that would allow guests to make arbitrary changes to pagetables, rather
      > than have them mediated by the hypervisor).
      
      Instead of making init a two pass sequence, to satisfy the Intel's TLB
      Application note (developer.intel.com/design/processor/applnots/317080.pdf
      Section 6 page 26), we preserve the original page permissions
      when fragmenting the large mappings and don't touch the existing memory
      mapping (which satisfies Xen's requirements).
      
      Only open issue is: on a native linux kernel, we will go back to mapping
      the first 0-1GB kernel identity mapping as executable (because of the
      static mapping setup in head_64.S). We can fix this in a different
      patch if needed.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Acked-by: NJeremy Fitzhardinge <jeremy@goop.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      b27a43c1
    • I
      x86, pat: cleanups · ad2cde16
      Ingo Molnar 提交于
      clean up recently added code to be more consistent with other x86 code.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ad2cde16
    • S
      x86: fix pagetable init 64-bit breakage · 28dd033f
      Suresh Siddha 提交于
      Fix _end alignment check - can trigger a crash if _end happens to be
      on a page boundary.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      28dd033f
    • S
      x86: track memtype for RAM in page struct · 9542ada8
      Suresh Siddha 提交于
      Track the memtype for RAM pages in page struct instead of using the
      memtype list. This avoids the explosion in the number of entries in
      memtype list (of the order of 20,000 with AGP) and makes the PAT
      tracking simpler.
      
      We are using PG_arch_1 bit in page->flags.
      
      We still use the memtype list for non RAM pages.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      9542ada8
    • S
      x86, cpa: srlz cpa(), global flush tlb after splitting big page and before doing cpa · ad5ca55f
      Suresh Siddha 提交于
      Do a global flush tlb after splitting the large page and before we do the
      actual change page attribute in the PTE.
      
      With out this, we violate the TLB application note, which says
          "The TLBs may contain both ordinary and large-page translations for
           a 4-KByte range of linear addresses. This may occur if software
           modifies the paging structures so that the page size used for the
           address range changes. If the two translations differ with respect
           to page frame or attributes (e.g., permissions), processor behavior
           is undefined and may be implementation-specific."
      
      And also serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity
      mappings) using cpa_lock. So that we don't allow any other cpu, with stale
      large tlb entries change the page attribute in parallel to some other cpu
      splitting a large page entry along with changing the attribute.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: arjan@linux.intel.com
      Cc: venkatesh.pallipadi@intel.com
      Cc: jeremy@goop.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ad5ca55f
    • S
      x86, cpa: remove cpa pool code · 8311eb84
      Suresh Siddha 提交于
      Interrupt context no longer splits large page in cpa(). So we can do away
      with cpa memory pool code.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: arjan@linux.intel.com
      Cc: venkatesh.pallipadi@intel.com
      Cc: jeremy@goop.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8311eb84
    • S
      x86, cpa: no need to check alias for __set_pages_p/__set_pages_np · 55121b43
      Suresh Siddha 提交于
      No alias checking needed for setting present/not-present mapping. Otherwise,
      we may need to break large pages for 64-bit kernel text mappings (this adds to
      complexity if we want to do this from atomic context especially, for ex:
      with CONFIG_DEBUG_PAGEALLOC). Let's keep it simple!
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: arjan@linux.intel.com
      Cc: venkatesh.pallipadi@intel.com
      Cc: jeremy@goop.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      55121b43
    • S
      x86, cpa: dont use large pages for kernel identity mapping with DEBUG_PAGEALLOC · 0b8fdcbc
      Suresh Siddha 提交于
      Don't use large pages for kernel identity mapping with DEBUG_PAGEALLOC.
      This will remove the need to split the large page for the
      allocated kernel page in the interrupt context.
      
      This will simplify cpa code(as we don't do the split any more from the
      interrupt context). cpa code simplication in the subsequent patches.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: arjan@linux.intel.com
      Cc: venkatesh.pallipadi@intel.com
      Cc: jeremy@goop.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      0b8fdcbc
    • S
      x86, cpa: make the kernel physical mapping initialization a two pass sequence · a2699e47
      Suresh Siddha 提交于
      In the first pass, kernel physical mapping will be setup using large or
      small pages but uses the same PTE attributes as that of the early
      PTE attributes setup by early boot code in head_[32|64].S
      
      After flushing TLB's, we go through the second pass, which setups the
      direct mapped PTE's with the appropriate attributes (like NX, GLOBAL etc)
      which are runtime detectable.
      
      This two pass mechanism conforms to the TLB app note which says:
      
      "Software should not write to a paging-structure entry in a way that would
       change, for any linear address, both the page size and either the page frame
       or attributes."
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: arjan@linux.intel.com
      Cc: venkatesh.pallipadi@intel.com
      Cc: jeremy@goop.org
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a2699e47
  5. 30 9月, 2008 1 次提交
  6. 15 9月, 2008 1 次提交
  7. 07 9月, 2008 4 次提交
  8. 05 9月, 2008 4 次提交
  9. 23 8月, 2008 1 次提交
  10. 22 8月, 2008 4 次提交
  11. 21 8月, 2008 2 次提交