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  1. 05 9月, 2013 1 次提交
  3. 21 8月, 2013 2 次提交
    • S
      powerpc: Convert some mftb/mftbu into mfspr · beb2dc0a
      由 Scott Wood 提交于 
      Some CPUs (such as e500v1/v2) don't implement mftb and will take a
trap.  mfspr should work on everything that has a timebase, and is the
preferred instruction according to ISA v2.06.

Currently we get away with mftb on 85xx because the assembler converts
it to mfspr due to -Wa,-me500.  However, that flag has other effects
that are undesireable for certain targets (e.g.  lwsync is converted to
sync), and is hostile to multiplatform kernels.  Thus we would like to
stop setting it for all e500-family builds.

mftb/mftbu instances which are in 85xx code or common code are
converted.  Instances which will never run on 85xx are left alone.
Signed-off-by: NScott Wood <scottwood@freescale.com>
      beb2dc0a
    • S
      powerpc/fsl-booke: Work around erratum A-006958 · d52459ca
      由 Scott Wood 提交于 
      Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject
to a similar race condition as doing mftbu/mftbl on 32-bit.  The lower
half of timebase is updated before the upper half; thus, we can share
the workaround for a similar bug on Cell.  This workaround involves
looping if the lower half of timebase is zero, thus avoiding the need
for a scratch register (other than CR0).  This workaround must be
avoided when the timebase is frozen, such as during the timebase sync
code.

This deals with kernel and vdso accesses, but other userspace accesses
will of course need to be fixed elsewhere.
Signed-off-by: NScott Wood <scottwood@freescale.com>
      d52459ca
  5. 14 8月, 2013 1 次提交
  7. 09 8月, 2013 1 次提交
  9. 24 7月, 2013 1 次提交
  11. 01 7月, 2013 2 次提交
  13. 01 6月, 2013 3 次提交
  15. 02 5月, 2013 3 次提交
  17. 27 4月, 2013 1 次提交
    • P
      KVM: PPC: Book3S HV: Improve real-mode handling of external interrupts · 4619ac88
      由 Paul Mackerras 提交于 
      This streamlines our handling of external interrupts that come in
while we're in the guest.  First, when waking up a hardware thread
that was napping, we split off the "napping due to H_CEDE" case
earlier, and use the code that handles an external interrupt (0x500)
in the guest to handle that too.  Secondly, the code that handles
those external interrupts now checks if any other thread is exiting
to the host before bouncing an external interrupt to the guest, and
also checks that there is actually an external interrupt pending for
the guest before setting the LPCR MER bit (mediated external request).

This also makes sure that we clear the "ceded" flag when we handle a
wakeup from cede in real mode, and fixes a potential infinite loop
in kvmppc_run_vcpu() which can occur if we ever end up with the ceded
flag set but MSR[EE] off.
Signed-off-by: NPaul Mackerras <paulus@samba.org>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      4619ac88
  19. 26 4月, 2013 2 次提交
  21. 18 4月, 2013 1 次提交
  23. 05 3月, 2013 1 次提交
  25. 15 2月, 2013 3 次提交
  27. 13 2月, 2013 1 次提交
  29. 08 2月, 2013 1 次提交
  31. 10 1月, 2013 4 次提交
  33. 06 12月, 2012 1 次提交
    • P
      KVM: PPC: Book3S PR: Fix VSX handling · 28c483b6
      由 Paul Mackerras 提交于 
      This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines.  First, we were running off the end
of the current->thread.fpr[] array.  Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).

Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction.  This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.

In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX.  Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest.  Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.

To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements.  Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: NPaul Mackerras <paulus@samba.org>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      28c483b6
  35. 15 11月, 2012 2 次提交
  37. 27 9月, 2012 1 次提交
  39. 17 9月, 2012 1 次提交
  41. 10 9月, 2012 1 次提交
  43. 07 9月, 2012 1 次提交
  45. 05 9月, 2012 3 次提交
  47. 11 7月, 2012 2 次提交