1. 27 4月, 2011 1 次提交
  2. 20 4月, 2011 4 次提交
  3. 01 4月, 2011 1 次提交
    • B
      powerpc/pmac/smp: Properly NAP offlined CPU on G5 · 62cc67b9
      Benjamin Herrenschmidt 提交于
      The current code soft-disables, and then goes to NAP mode which
      turns interrupts on. That means that if an interrupt occurs, we
      will hit the masked interrupt code path which isn't what we want,
      as it will return with EE off, which will either get us out of
      NAP mode, or fail to enter it (according to spec).
      
      Instead, let's just rely on the fact that it is safe to take
      decrementer interrupts on an offline CPU and leave interrupts
      enabled. We can also get rid of the special case in asm for
      power4_cpu_offline_powersave() and just use power4_idle().
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      62cc67b9
  4. 31 3月, 2011 1 次提交
  5. 09 12月, 2010 1 次提交
  6. 29 11月, 2010 1 次提交
  7. 24 10月, 2010 1 次提交
  8. 31 8月, 2010 1 次提交
    • M
      powerpc: Don't use kernel stack with translation off · 54a83404
      Michael Neuling 提交于
      In f761622e we changed
      early_setup_secondary so it's called using the proper kernel stack
      rather than the emergency one.
      
      Unfortunately, this stack pointer can't be used when translation is off
      on PHYP as this stack pointer might be outside the RMO.  This results in
      the following on all non zero cpus:
        cpu 0x1: Vector: 300 (Data Access) at [c00000001639fd10]
            pc: 000000000001c50c
            lr: 000000000000821c
            sp: c00000001639ff90
           msr: 8000000000001000
           dar: c00000001639ffa0
         dsisr: 42000000
          current = 0xc000000016393540
          paca    = 0xc000000006e00200
            pid   = 0, comm = swapper
      
      The original patch was only tested on bare metal system, so it never
      caught this problem.
      
      This changes __secondary_start so that we calculate the new stack
      pointer but only start using it after we've called early_setup_secondary.
      
      With this patch, the above problem goes away.
      Signed-off-by: NMichael Neuling <mikey@neuling.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      54a83404
  9. 24 8月, 2010 1 次提交
    • M
      powerpc: Initialise paca->kstack before early_setup_secondary · f761622e
      Matt Evans 提交于
      As early setup calls down to slb_initialize(), we must have kstack
      initialised before checking "should we add a bolted SLB entry for our kstack?"
      
      Failing to do so means stack access requires an SLB miss exception to refill
      an entry dynamically, if the stack isn't accessible via SLB(0) (kernel text
      & static data).  It's not always allowable to take such a miss, and
      intermittent crashes will result.
      
      Primary CPUs don't have this issue; an SLB entry is not bolted for their
      stack anyway (as that lives within SLB(0)).  This patch therefore only
      affects the init of secondaries.
      Signed-off-by: NMatt Evans <matt@ozlabs.org>
      Cc: stable <stable@kernel.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      f761622e
  10. 17 5月, 2010 1 次提交
  11. 09 3月, 2010 2 次提交
  12. 05 11月, 2009 1 次提交
  13. 20 8月, 2009 3 次提交
    • B
      powerpc: Remaining 64-bit Book3E support · 2d27cfd3
      Benjamin Herrenschmidt 提交于
      This contains all the bits that didn't fit in previous patches :-) This
      includes the actual exception handlers assembly, the changes to the
      kernel entry, other misc bits and wiring it all up in Kconfig.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      2d27cfd3
    • B
      powerpc: Use names rather than numbers for SPRGs (v2) · ee43eb78
      Benjamin Herrenschmidt 提交于
      The kernel uses SPRG registers for various purposes, typically in
      low level assembly code as scratch registers or to hold per-cpu
      global infos such as the PACA or the current thread_info pointer.
      
      We want to be able to easily shuffle the usage of those registers
      as some implementations have specific constraints realted to some
      of them, for example, some have userspace readable aliases, etc..
      and the current choice isn't always the best.
      
      This patch should not change any code generation, and replaces the
      usage of SPRN_SPRGn everywhere in the kernel with a named replacement
      and adds documentation next to the definition of the names as to
      what those are used for on each processor family.
      
      The only parts that still use the original numbers are bits of KVM
      or suspend/resume code that just blindly needs to save/restore all
      the SPRGs.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ee43eb78
    • B
      powerpc: Rename exception.h to exception-64s.h · 8aa34ab8
      Benjamin Herrenschmidt 提交于
      The file include/asm/exception.h contains definitions
      that are specific to exception handling on 64-bit server
      type processors.
      
      This renames the file to exception-64s.h to reflect that
      fact and avoid confusion.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8aa34ab8
  14. 09 6月, 2009 2 次提交
  15. 11 3月, 2009 1 次提交
    • B
      powerpc/kconfig: Kill PPC_MULTIPLATFORM · 28794d34
      Benjamin Herrenschmidt 提交于
      CONFIG_PPC_MULTIPLATFORM is a remain of the pre-powerpc days and isn't
      really meaningful anymore. It was basically equivalent to PPC64 || 6xx.
      
      This removes it along with the following changes:
      
       - 32-bit platforms that relied on PPC32 && PPC_MULTIPLATFORM now rely
         on 6xx which is what they want anyway.
      
       - A new symbol, PPC_BOOK3S, is defined that represent compliance with
         the "Server" variant of the architecture. This is set when either 6xx
         or PPC64 is set and open the door for future BOOK3E 64-bit.
      
       - 64-bit platforms that relied on PPC64 && PPC_MULTIPLATFORM now use
         PPC64 && PPC_BOOK3S
      
       - A separate and selectable CONFIG_PPC_OF_BOOT_TRAMPOLINE option is now
         used to control the use of prom_init.c
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      28794d34
  16. 13 1月, 2009 1 次提交
    • B
      powerpc/powermac: Fix occasional SMP boot failure · c478b581
      Benjamin Herrenschmidt 提交于
      The PowerMac kernel occasionally fails to bring up the secondary CPUs on
      SMP, the trigger factor seem to be fairly random and related to location
      of code and data.
      
      This appears to be due to the initial loading of the TOC value by the
      secondary processor which now happens before we clear HID4:RM_CI (Real
      Mode Cache Invalidate). This bit should really be cleared before we do
      any load or store other than fetching code.
      
      This fix works based on the assumption that all SMP 64-bit PowerMacs use
      variants of the 970, which fortunately is true, by explicitely clearing
      that bit, adding an slbia for good measure as RM_CI mode is known to
      create bogus ERAT entries.
      
      I also removed some spurrious debug output that was left enabled by
      mistake while at it.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      c478b581
  17. 31 10月, 2008 1 次提交
    • M
      powerpc/ppc64/kdump: Better flag for running relocatable · 8b8b0cc1
      Milton Miller 提交于
      The __kdump_flag ABI is overly constraining for future development.
      
      As of 2.6.27, the kernel entry point has 4 constraints:  Offset 0 is
      the starting point for the master (boot) cpu (entered with r3 pointing
      to the device tree structure), offset 0x60 is code for the slave cpus
      (entered with r3 set to their device tree physical id), offset 0x20 is
      used by the iseries hypervisor, and secondary cpus must be well behaved
      when the first 256 bytes are copied to address 0.
      
      Placing the __kdump_flag at 0x18 is bad because:
      
      - It was taking the last 8 bytes before the iseries hypervisor data.
      - It was 8 bytes for a boolean flag
      - It had no way of identifying that the flag was present
      - It does leave any room for the master to add any additional code
        before branching, which hurts debug.
      - It will be unnecessarily hard for 32 bit code to be common (8 bytes)
      
      Now that we have eliminated the use of __kdump_flag in favor of
      the standard is_kdump_kernel(), this flag only controls run without
      relocating the kernel to PHYSICAL_START (0), so rename it __run_at_load.
      
      Move the flag to 0x5c, 1 word before the secondary cpu entry point at
      0x60.  Initialize it with "run0" to say it will run at 0 unless it is
      set to 1.  It only exists if we are relocatable.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NMichael Neuling <mikey@neuling.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      8b8b0cc1
  18. 22 10月, 2008 1 次提交
    • M
      powerpc: Support for relocatable kdump kernel · 54622f10
      Mohan Kumar M 提交于
      This adds relocatable kernel support for kdump. With this one can
      use the same regular kernel to capture the kdump. A signature (0xfeed1234)
      is passed in r6 from panic code to the next kernel through kexec_sequence
      and purgatory code. The signature is used to differentiate between
      kdump kernel and non-kdump kernels.
      
      The purgatory code compares the signature and sets the __kdump_flag in
      head_64.S.  During the boot up, kernel code checks __kdump_flag and if it
      is set, the kernel will behave as relocatable kdump kernel. This kernel
      will boot at the address where it was loaded by kexec-tools ie. at the
      address reserved through crashkernel boot parameter.
      
      CONFIG_CRASH_DUMP depends on CONFIG_RELOCATABLE option to build kdump
      kernel as relocatable. So the same kernel can be used as production and
      kdump kernel.
      
      This patch incorporates the changes suggested by Paul Mackerras to avoid
      GOT use and to avoid two copies of the code.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NMohan Kumar M <mohan@in.ibm.com>
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      54622f10
  19. 16 9月, 2008 4 次提交
    • P
      powerpc: Make the 64-bit kernel as a position-independent executable · 549e8152
      Paul Mackerras 提交于
      This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
      a position-independent executable (PIE) when it is set.  This involves
      processing the dynamic relocations in the image in the early stages of
      booting, even if the kernel is being run at the address it is linked at,
      since the linker does not necessarily fill in words in the image for
      which there are dynamic relocations.  (In fact the linker does fill in
      such words for 64-bit executables, though not for 32-bit executables,
      so in principle we could avoid calling relocate() entirely when we're
      running a 64-bit kernel at the linked address.)
      
      The dynamic relocations are processed by a new function relocate(addr),
      where the addr parameter is the virtual address where the image will be
      run.  In fact we call it twice; once before calling prom_init, and again
      when starting the main kernel.  This means that reloc_offset() returns
      0 in prom_init (since it has been relocated to the address it is running
      at), which necessitated a few adjustments.
      
      This also changes __va and __pa to use an equivalent definition that is
      simpler.  With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
      constants (for 64-bit) whereas PHYSICAL_START is a variable (and
      KERNELBASE ideally should be too, but isn't yet).
      
      With this, relocatable kernels still copy themselves down to physical
      address 0 and run there.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      549e8152
    • P
      powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bit · e31aa453
      Paul Mackerras 提交于
      Using LOAD_REG_IMMEDIATE to get the address of kernel symbols
      generates 5 instructions where LOAD_REG_ADDR can do it in one,
      and will generate R_PPC64_ADDR16_* relocations in the output when
      we get to making the kernel as a position-independent executable,
      which we'd rather not have to handle.  This changes various bits
      of assembly code to use LOAD_REG_ADDR when we need to get the
      address of a symbol, or to use suitable position-independent code
      for cases where we can't access the TOC for various reasons, or
      if we're not running at the address we were linked at.
      
      It also cleans up a few minor things; there's no reason to save and
      restore SRR0/1 around RTAS calls, __mmu_off can get the return
      address from LR more conveniently than the caller can supply it in
      R4 (and we already assume elsewhere that EA == RA if the MMU is on
      in early boot), and enable_64b_mode was using 5 instructions where
      2 would do.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      e31aa453
    • P
      powerpc: Make it possible to move the interrupt handlers away from the kernel · 1f6a93e4
      Paul Mackerras 提交于
      This changes the way that the exception prologs transfer control to
      the handlers in 64-bit kernels with the aim of making it possible to
      have the prologs separate from the main body of the kernel.  Now,
      instead of computing the address of the handler by taking the top
      32 bits of the paca address (to get the 0xc0000000........ part) and
      ORing in something in the bottom 16 bits, we get the base address of
      the kernel by doing a load from the paca and add an offset.
      
      This also replaces an mfmsr and an ori to compute the MSR value for
      the handler with a load from the paca.  That makes it unnecessary to
      have a separate version of EXCEPTION_PROLOG_PSERIES that forces 64-bit
      mode.
      
      We can no longer use a direct branches in the exception prolog code,
      which means that the SLB miss handlers can't branch directly to
      .slb_miss_realmode any more.  Instead we have to compute the address
      and do an indirect branch.  This is conditional on CONFIG_RELOCATABLE;
      for non-relocatable kernels we use a direct branch as before.  (A later
      change will allow CONFIG_RELOCATABLE to be set on 64-bit powerpc.)
      
      Since the secondary CPUs on pSeries start execution in the first 0x100
      bytes of real memory and then have to get to wherever the kernel is,
      we can't use a direct branch to get there.  Instead this changes
      __secondary_hold_spinloop from a flag to a function pointer.  When it
      is set to a non-NULL value, the secondary CPUs jump to the function
      pointed to by that value.
      
      Finally this eliminates one code difference between 32-bit and 64-bit
      by making __secondary_hold be the text address of the secondary CPU
      spinloop rather than a function descriptor for it.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      1f6a93e4
    • P
      powerpc: Rearrange head_64.S to move interrupt handler code to the beginning · 9a955167
      Paul Mackerras 提交于
      This rearranges head_64.S so that we have all the first-level exception
      prologs together starting at 0x100, followed by all the second-level
      handlers that are invoked from the first-level prologs, followed by
      other code.  This doesn't make any functional change but will make
      following changes for relocatable kernel support easier.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      9a955167
  20. 15 7月, 2008 1 次提交
  21. 01 7月, 2008 3 次提交
  22. 09 5月, 2008 1 次提交
  23. 29 4月, 2008 1 次提交
    • P
      [POWERPC] Add fast little-endian switch system call · 745a14cc
      Paul Mackerras 提交于
      This adds a system call on 64-bit platforms for switching between
      little-endian and big-endian modes that is much faster than doing a
      prctl call.  This system call is handled as a special case right at
      the start of the system call entry code, and because it is a special
      case, it uses a system call number which is out of the range of
      normal system calls, namely 0x1ebe.
      
      Measurements with lmbench on a 4.2GHz POWER6 showed no measurable
      change in the speed of normal system calls with this patch.
      
      Switching endianness with this new system call takes around 60ns on a
      4.2GHz POWER6, compared with around 300ns to switch endian mode with a
      prctl.  This can provide a significant performance advantage for
      emulators for little-endian architectures that want to switch between
      big-endian and little-endian mode frequently, e.g. because they are
      generating instructions sequences on the fly and they want to run
      those sequences in little-endian mode.
      
      The other thing about this system call is that it doesn't clobber as
      many registers as a normal system call.  It only clobbers r12.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      745a14cc
  24. 18 4月, 2008 1 次提交
  25. 17 4月, 2008 1 次提交
  26. 14 4月, 2008 1 次提交
    • P
      [POWERPC] Fix handling of unrecoverable SLB miss interrupts · 320787c7
      Paul Mackerras 提交于
      If an SLB miss interrupt happens while the RI bit of MSR is zero, we
      can't just return, because RI being zero indicates that SRR0/SRR1
      potentially had live values in them, and the process of taking an
      interrupt overwrites them.
      
      This should never happen, but if it does, we try to print a nice oops
      message.  That doesn't work, however, because the code at unrecov_slb
      assumes that the MMU has been turned on, but we call it with the MMU
      off (and have done so since the SLB miss handler was rewritten to run
      without turning the MMU on) -- except on iSeries, where everything runs
      with the MMU on.
      
      This fixes it by adding the necessary code to turn the MMU on if
      necessary.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      320787c7
  27. 03 4月, 2008 1 次提交
    • B
      [POWERPC] Fix iSeries hard irq enabling regression · ff3da2e0
      Benjamin Herrenschmidt 提交于
      A subtle bug sneaked into iSeries recently.  On this platform, we must
      not normally clear MSR:EE (the hardware external interrupt enable)
      except for short periods of time.  Taking an interrupt while
      soft-disabled doesn't cause us to clear it for example.
      
      The iSeries kernel expects to mostly run with MSR:EE enabled at all
      times except in a few exception entry/exit code paths.  Thus
      local_irq_enable() doesn't check if it needs to hard-enable as it
      expects this to be unnecessary on iSeries.
      
      However, hard_irq_disable() _does_ cause MSR:EE to be cleared,
      including on iSeries.  A call to it was recently added to the
      context switch code, thus causing interrupts to become disabled
      for a long periods of time, causing the iSeries watchdog to kick
      in under some circumstances and other nasty things.
      
      This patch fixes it by making local_irq_enable() properly re-enable
      MSR:EE on iSeries.  It basically removes a return statement here
      to make iSeries use the same code path as everybody else.  That does
      mean that we might occasionally get spurious decrementer interrupts
      but I don't think that matters.
      
      Another option would have been to make hard_irq_disable() a nop
      on iSeries but I didn't like it much, in case we have good reasons
      to hard-disable.
      
      Part of the patch is fixes to make sure the hard_enabled PACA field
      is properly set on iSeries as it used not to be before, since it
      was mostly unused.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      ff3da2e0
  28. 24 1月, 2008 1 次提交
    • P
      [POWERPC] Provide a way to protect 4k subpages when using 64k pages · fa28237c
      Paul Mackerras 提交于
      Using 64k pages on 64-bit PowerPC systems makes life difficult for
      emulators that are trying to emulate an ISA, such as x86, which use a
      smaller page size, since the emulator can no longer use the MMU and
      the normal system calls for controlling page protections.  Of course,
      the emulator can emulate the MMU by checking and possibly remapping
      the address for each memory access in software, but that is pretty
      slow.
      
      This provides a facility for such programs to control the access
      permissions on individual 4k sub-pages of 64k pages.  The idea is
      that the emulator supplies an array of protection masks to apply to a
      specified range of virtual addresses.  These masks are applied at the
      level where hardware PTEs are inserted into the hardware page table
      based on the Linux PTEs, so the Linux PTEs are not affected.  Note
      that this new mechanism does not allow any access that would otherwise
      be prohibited; it can only prohibit accesses that would otherwise be
      allowed.  This new facility is only available on 64-bit PowerPC and
      only when the kernel is configured for 64k pages.
      
      The masks are supplied using a new subpage_prot system call, which
      takes a starting virtual address and length, and a pointer to an array
      of protection masks in memory.  The array has a 32-bit word per 64k
      page to be protected; each 32-bit word consists of 16 2-bit fields,
      for which 0 allows any access (that is otherwise allowed), 1 prevents
      write accesses, and 2 or 3 prevent any access.
      
      Implicit in this is that the regions of the address space that are
      protected are switched to use 4k hardware pages rather than 64k
      hardware pages (on machines with hardware 64k page support).  In fact
      the whole process is switched to use 4k hardware pages when the
      subpage_prot system call is used, but this could be improved in future
      to switch only the affected segments.
      
      The subpage protection bits are stored in a 3 level tree akin to the
      page table tree.  The top level of this tree is stored in a structure
      that is appended to the top level of the page table tree, i.e., the
      pgd array.  Since it will often only be 32-bit addresses (below 4GB)
      that are protected, the pointers to the first four bottom level pages
      are also stored in this structure (each bottom level page contains the
      protection bits for 1GB of address space), so the protection bits for
      addresses below 4GB can be accessed with one fewer loads than those
      for higher addresses.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fa28237c