Kurobox Pro/Linkstation Pro devices use a microcontroller connected
to UART1.  As most of the communication with this microcontroller is
done from userland (power button detection, fan speed ...), the setup
file has to make UART1 available from userland.
Signed-off-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.

This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: NStanislav Samsonov <samsonov@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either
be used in x4 mode or in quad x1 mode.  This patch adds an accessor
function to the generic plat-orion PCIe handling code to detect in
which of the two modes we're running (which is determined by strap
pins and/or configured by the bootloader).
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Add support for the Feroceon 88fr571-vd CPU core as found in e.g.
the Marvell Discovery Duo family of ARM SoCs.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.

This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Add support for the Shiva 88fr131 CPU core as found in e.g. the
Marvell Kirkwood family of ARM SoCs.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.

Note that:

- Page table walks are outer uncacheable on Kirkwood and Discovery
  Duo, since the ARMv5 spec provides no way to indicate outer
  cacheability of page table walks (specifying it in TTBR[4:3] is
  an ARMv6+ feature).

  This requires adding L2 cache clean instructions to
  proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
  tlbflush.h ({flush,clean}_pmd_entry()).  The latter case is handled
  by defining a new TLB type (TLB_FEROCEON) which is almost identical
  to the v4wbi one but provides a TLB_L2CLEAN_FR flag.

- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
  range by MVA' and 'invalidate L2 range by MVA') operations, and this
  patch uses those range operations for all Linux outer cache
  operations, as they are faster than the regular per-line operations.

  L2 range operations are not interruptible on this hardware, which
  avoids potential livelock issues, but can be bad for interrupt
  latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
  allows you to select the maximum range size to operate on at once.
  (Valid range is between one cache line and one 4KiB page, and must
  be a multiple of the line size.)
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.
Signed-off-by: NStanislav Samsonov <samsonov@marvell.com>
Acked-by: NSaeed Bishara <saeed@marvell.com>
Reviewed-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.

This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.

This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

There are a couple more Feroceon-based SoCs out in the field that use
different Variant and Architecture fields in their Main ID registers
-- this patch tweaks the processor match/mask in proc-feroceon.S to
catch those SoCs as well.
Signed-off-by: NKe Wei <kewei@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Tweak the Feroceon match/mask in arch/arm/boot/compressed/head.S to
match a couple of newer Feroceon cores (such as the 88fr571vd with
CPU ID 0x56155710, and the 88fr131 with CPU ID 0x56251310) as well.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.

This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Nuke the Orion-specific orion5x_{read,write} wrappers.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch adds support for the Maxtor Shared Storage II hardware.
Signed-off-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Tested-by: NDirk Teurlings <dirk@upexia.nl>
Tested-by: NPeter van Valderen <p.v.valderen@gmail.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch implements the communication with the microcontroller on the
Kurobox Pro and Linkstation Pro/Live boards.  This is allowing to send
the commands needed to power-off the board correctly.
Signed-off-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The mv643xx_eth platform data field ->force_phy_addr only needs
to be set if the passed-in ->phy_addr field is zero (to distinguish
the case of not having specified a phy address
(force_phy_addr = 0) from the case where a phy address of zero needs
to be used (force_phy_addr = 1.))

Also, the ->force_phy_addr field will hopefully disappear in a
future mv643xx_eth reorganisation.

Therefore, this patch deletes the ->force_phy_addr field initialiser
from all Orion board code.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

If all PCI devices are working as expected, the error printks in the
various implementations of ->map_irq() doesn't really provide any
useful info.  And if something is not working as expected, turning
on pci=debug gives you more useful information than the printk calls
in ->map_irq(), since the former also tells you which devices _did_
get IRQs successfully assigned.  Therefore, delete these printks
entirely.

Spotted by Russell King.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

Instead of having board code poke directly into the MPP configuration
registers, and separately calling orion5x_gpio_set_valid_pins() to
indicate which MPP pins can be used as GPIO pins, introduce a helper
function for configuring the roles of each of the MPP pins, and have
that helper function handle gpio validity internally.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NSylver Bruneau <sylver.bruneau@googlemail.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

It makes no sense to do PCIe WA window setup in the individual
board support files while the decision whether or not to use the
PCIe WA access method is made in a different place, in the PCIe
support code.

This patch moves the configuration of a PCIe WA window from the
individual Orion board support files to the central Orion PCIe
support code.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

This patch moves initialisation of EHCI/I2C/UART platform devices
from the common orion5x_init() into the board support code.

The rationale behind this is that only the board support code knows
whether certain peripherals have been brought out on the board, and
not initialising peripherals that haven't been brought out is
desirable for example:
- to reduce user confusion (e.g. seeing both 'eth0' and 'eth1'
  appear while there is only one ethernet port on the board); and
- to allow for future power savings (peripherals that have not
  been brought out can be clock gated off entirely).
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

This define isn't used anywhere in the kernel tree -- nuke it.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

Make it clear that Orion top-level IRQs are level-triggered.  This
means that we don't need an ->ack() handler, or at least, we don't
need the ->ack() handler (or the acking part of the ->mask_ack()
handler) to actually do anything.

Given that, we might as well point our ->mask_ack() handler at the
->mask() handler instead of providing a dummy ->ack() handler, since
providing a ->mask_ack() handler on level IRQ sources will prevent
->ack() from ever being called.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

Annotate the entries for the 88fr531-vd CPU core in
arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S
with the full name of the core.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

The DRAM base address and size fields in the CPU's MBUS bridge have
64KiB granularity, instead of the currently used 16MiB.  Since all
of the currently supported MBUS peripherals support 64KiB granularity
as well, this patch changes the Orion address map code to stop
rounding base addresses down and sizes up to multiples of 16MiB.

Found by Ke Wei <kewei@marvell.com>.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

Currently, Orion window setup uses hardcoded window indexes for each
of the boot/cs0/cs1/cs2/PCIe WA windows.  The static window allocation
used can clash if board support code will ever attempt to configure
both a dev2 and a PCIe WA window, as both of those use CPU mbus window
#7 at present.

This patch keeps track of the last used window, and opens subsequently
requested windows sequentially, starting from 4.  (Windows 0-3 are used
as MEM/IO windows for the PCI/PCIe buses.)
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

More cosmetic cleanup:
- Replace 8-space indents by proper tab indents.
- In structure initialisers, use a trailing comma for every member.
- Collapse "},\n{" in structure initialiers to "}, {".
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>

This is a natural extension following the previous patch.
Non Feroceon based targets are unchanged.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The implementation for memory copy functions on ARM had a (disabled)
provision for aligning the source pointer before loading registers with
data.  Turns out that aligning the _destination_ pointer is much more
useful, as the read side is already sufficiently helped with the use of
preload.

So this changes the definition of the CALGN() macro to target the
destination pointer instead, and turns it on for Feroceon processors
where the gain is very noticeable.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This code is currently disabled, which explains why no one was affected.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>