The core page allocator ensures that page flags are zeroed when freeing
pages via free_pages_check.  A number of architectures (ARM, PPC, MIPS)
rely on this property to treat new pages as dirty with respect to the data
cache and perform the appropriate flushing before mapping the pages into
userspace.

This can lead to cache synchronisation problems when using hugepages,
since the allocator keeps its own pool of pages above the usual page
allocator and does not reset the page flags when freeing a page into the
pool.

This patch adds a new architecture hook, arch_clear_hugepage_flags, so
that architectures which rely on the page flags being in a particular
state for fresh allocations can adjust the flags accordingly when a page
is freed into the pool.
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Cc: Michal Hocko <mhocko@suse.cz>
Reviewed-by: NMichal Hocko <mhocko@suse.cz>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This is a preparatory patch for the introduction of NT_SIGINFO elf note.

Make the location of compat_siginfo_t uniform across eight architectures
which have it.  Now it can be pulled in by including asm/compat.h or
linux/compat.h.

Most of the copies are verbatim.  compat_uid[32]_t had to be replaced by
__compat_uid[32]_t.  compat_uptr_t had to be moved up before
compat_siginfo_t in asm/compat.h on a several architectures (tile already
had it moved up).  compat_sigval_t had to be relocated from linux/compat.h
to asm/compat.h.
Signed-off-by: NDenys Vlasenko <vda.linux@googlemail.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Amerigo Wang <amwang@redhat.com>
Cc: "Jonathan M. Foote" <jmfoote@cert.org>
Cc: Roland McGrath <roland@hack.frob.com>
Cc: Pedro Alves <palves@redhat.com>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Convert #include "..." to #include <path/...> in kernel system headers.
Signed-off-by: NDavid Howells <dhowells@redhat.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: NDave Jones <davej@redhat.com>

Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.

Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The MIPSsim platform is no longer supported or used.

[ralf@linux-mips.org: Also remove mipssim from arch/mips/Kbuild.platforms
and delete arch/mips/include/asm/mach-mipssim/*.]
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4350/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

If it's set, SIGPENDING is also set.  And SIGPENDING is present in
the masks...
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Acked-by: NDavid Daney <david.daney@cavium.com>

Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Acked-by: NDavid Daney <david.daney@cavium.com>

These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

Fix whitespace, beautify the code and remove debug statements.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

The GIC interrupt code is used by multiple platforms and the
current code was half Malta dependent code. These changes
abstract away the platform specific differences.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

More information about the SEAD-3 platform can be found at
<http://www.mips.com/products/development-kits/mips-sead-3/>
on MTI's site. Currently, the M14K family of cores is what
the SEAD-3 is utilised with.
Signed-off-by: NDouglas Leung <douglas@mips.com>
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

Signed-off-by: NSteven J. Hill <sjhill@mips.com>

The gpio_chip struct allows us to set a .to_irq callback. Once this is set
we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing
more than one gpio_chip to register an interrupt
Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org

Also cleanup and fix octeon_init_cvmcount()
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>

The cn68XX has a new interrupt controller named CIU2, add support for
this, and use it if cn68XX detected at runtime.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

There are 64 workqueue, 32 watchdog, and 4 mbox.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

Also add cvmx_get_octeon_family().

Both of these are needed by the upcoming register definition refresh
patch.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Reviewed-by: NJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4111/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4084/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

OHCI/EHCI are in the high (second) word.  Not currently used by any
driver.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4026/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

The USB 2.0 device depends on some functionality in other blocks, such
as GPIO and USBH.  Add those register definitions here.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4025/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4083/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

The "IUDMA" engine used by bcm63xx_enet is also used by other blocks,
such as the USB 2.0 device.  Move the definitions into a common file so
that they do not need to be duplicated in each driver.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4082/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4172/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

These were erroneously copied from BCM6368. BCM6328 does not expose the
ENETSW_TXDMA interrupts, and BCM_6328_HIGH_IRQ_BASE + 7 is actually used
for the second UART.
Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4090/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Add the missing definitions for BCM6345.
Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4091/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/

Needed by SPI driver.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/3796/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

The ath79 platform code allows to run a single kernel image on various
SoCs which are based on the 24Kc and 74Kc cores.  The current code
explicitely disables the DSP ASE, but that is available in the 74Kc core.

Remove the override in order to let the kernel to detect the availability
of the DSP ASE at runtime.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4222/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The current implementation of synchronise_count_{master,slave} blocks
slave CPUs in early boot until all of them come up. This no longer
works because blocking a CPU with interrupts off after notifying the
CPU to be online causes problems with the current kernel.

Specifically, after the workqueue changes
(commit a08489c5 "Pull workqueue changes from Tejun Heo")
the CPU_ONLINE notification callback workqueue_cpu_up_callback()
will hang on wait_for_completion(&idle_rebind.done), if the slave
CPUs are blocked for synchronize_count_slave().

The changes are to update synchronize_count_{master,slave}() to handle
one CPU at a time and to call synchronise_count_master() in __cpu_up()
so that the CPU_ONLINE notification goes out only after the COP0 COUNT
register is synchronized.

[ralf@linux-mips.org: This matter only to those few platforms which are
using the cp0 counter as their clocksource which are XLP, XLR and MIPS'
CMP solution.]
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4216/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

BCM6338 and BCM6348 have a message control register width of 8 bits, instead
of 16-bits like what the SPI driver assumes right now. Also the SPI message
type shift value of 14 is actually 6 for these SoCs.
This resulted in transmit FIFO corruption because we were writing 16-bits
to an 8-bits wide register, thus spanning on the first byte of the transmit
FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().

Fix this by passing the message control register width and message type
shift through platform data back to the SPI driver so that it can use
it properly.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Cc: jonas.gorski@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/3983/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The relocation code was essentially taken from the 2.4 modutils which
perform relocation in userspace.  In 2.6 relocation of multiple modules
may be performed in parallel by the in-kernel loader so the global
variable mips_hi16_list won't fly anymore.  Fix race by moving it into
mod_arch_specific.

[ralf@linux-mips.org: folded in Tony's followup fix.  Thanks Tony!]
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NTony Wu <tung7970@gmail.com>
Cc:  linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4189/

The AR724[12] SoCs have more GPIO lines than the AR7240.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Cc: linux-mips@linux-mips.org
Patchwork: https://http://patchwork.linux-mips.org/patch/4167/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Since 3.6.0-rc1,  We are getting many messages like:

WARNING: at kernel/irq/irqdomain.c:444 irq_domain_associate_many+0x23c/0x260()
Modules linked in:
Call Trace:
[<ffffffff814cb698>] dump_stack+0x8/0x34
[<ffffffff81133d00>] warn_slowpath_common+0x78/0xa8
[<ffffffff81187e44>] irq_domain_associate_many+0x23c/0x260
[<ffffffff81187f38>] irq_create_mapping+0xd0/0x220
[<ffffffff81188104>] irq_create_of_mapping+0x7c/0x158
[<ffffffff813e5f08>] irq_of_parse_and_map+0x28/0x40
.
.
.

Both the CIU and GPIO interrupt domains were somewhat screwed up.

For the CIU domain, we need to call irq_domain_associate() for each of
the preassigned irq numbers.  For the GPIO domain, we were applying
the register bit offset in octeon_irq_gpio_xlat, but it should be done
in octeon_irq_gpio_map instead.

Also: Reserve all 8 'core' irqs for the 'core' irq_chip so that they
don't get used by the other domains.  Remove unused OCTEON_IRQ_*
symbols.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4190/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For unexplainable reasons the Loongson 2 clock API was implemented in a
module so fixing this involved shifting large amounts of code around.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>