The functions in linux/of_pci.h are primarily used by host bridge
drivers, so they can be private to drivers/pci/.

The remaining functions are still used mostly in host bridge drivers
that still live in arch specific code. Hopefully someday, those will get
moved into drivers/pci as well.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Tegra186 powergate driver is implemented as power domain driver, power
partition ungate/gate are registered as power_on/power_off callback
functions. There are no direct functions to power gate/ungate host
controller in Tegra186. Host controller driver should add "power-domains"
property in device tree and implement runtime suspend and resume
callback functons. Power gate and ungate is taken care by power domain
driver when host controller driver calls pm_runtime_put_sync and
pm_runtime_get_sync respectively.

Register suspend_noirq & resume_noirq callback functions to allow PCIe to
come up after resume from RAM. Both runtime and noirq pm ops share same
callback functions.
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
[lorenzo.pieralisi@arm.com: squashed patch to fix compilation]
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>

Implement remove callback function for Tegra PCIe driver to add
loadable kernel module support.

Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port should broadcast PME_Turn_Off
message before PCIe link goes to L2. PME_Turn_Off broadcast mechanism is
implemented in AFI module. Each Tegra PCIe root port has its own
PME_Turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this
register to broadcast PME_Turn_Off message.

Once PME_TO_Ack is recieved driver will turn OFF PCIe clock, power gate
PCIe partition and turn OFF regulators.
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>

tegra_pcie_probe() can fail in multiple instances, this patch takes care
of freeing the resources which are allocated before probe fail.
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>

Add SPDX GPL-2.0+ to all PCI files that specified the GPL and allowed
either GPL version 2 or any later version.

Remove the boilerplate GPL version 2 or later language, relying on the
assertion in b2441318 ("License cleanup: add SPDX GPL-2.0 license
identifier to files with no license") that the SPDX identifier may be used
instead of the full boilerplate text.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Tegra host driver is using pci_find_host_bridge() to get private data;
this can be easily avoided by using bus->sysdata to store and get private
data removing the pci_find_host_bridge() dependency.
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
[lorenzo.pieralisi@arm.com: rewrote commit log]
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NThierry Reding <treding@nvidia.com>

Bridge primary, secondary, and subordinate bus numbers power up as zero,
and Tegra firmware doesn't program them.

pci_scan_bridge_extend() automatically programs these bus numbers if they
are zero, so we don't need to set the PCI_REASSIGN_ALL_BUS flag for Tegra.
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
[bhelgaas: changelog]
Signed-off-by: NBjorn Helgaas <helgaas@kernel.org>
Acked-by: NThierry Reding <treding@nvidia.com>

Use only 4 KiB space from the available 1 GiB PCIe aperture to access
endpoint configuration space by dynamically moving the AFI_FPCI_BAR base
address. This frees more space for mapping endpoint device BARs on some
Tegra platforms.

The ->add_bus() and ->remove_bus() callbacks are now no longer needed,
so they can be removed.
Signed-off-by: NVidya Sagar <vidyas@nvidia.com>
[treding@nvidia.com: various cleanups, update commit message]
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

On arm, PCI_REASSIGN_ALL_RSRC is used only in pcibios_assign_all_busses(),
which helps decide whether to reconfigure bridge bus numbers.  It has
nothing to do with BAR assignments.  On arm64 and powerpc,
pcibios_assign_all_busses() tests PCI_REASSIGN_ALL_BUS, which makes more
sense.

Align arm with arm64 and powerpc, so they all use PCI_REASSIGN_ALL_BUS for
pcibios_assign_all_busses().

Remove PCI_REASSIGN_ALL_RSRC from the generic, Tegra, Versatile, and
R-Car drivers.  These drivers are used only on arm or arm64, where
PCI_REASSIGN_ALL_RSRC is not used after this change, so removing it
should have no effect.

No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add Tegra186 PCIe support.  UPHY programming is performed by BPMP; PHY
enable calls are not required for Tegra186 PCIe.

Power partition ungate is done by BPMP powergate driver.  The Tegra186
DT description must include a "power-domains" property, which results in
dev->pm_domain being set.
Tested-by: NMikko Perttunen <mperttunen@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
[bhelgaas: add "power-domains" reference]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMikko Perttunen <mperttunen@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>

The Tegra PCI host controller can generate configuration space accesses
with byte, word and dword granularity for devices. Only root ports can't
have their configuration space accessed in this way.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

This reverts commit d7bd554f.

It turns out that Tegra20 has a bug in the implementation of the MSI
target address register (which is worked around by the existence of the
struct tegra_pcie_soc.msi_base_shift parameter) that restricts the MSI
target memory to the lower 32 bits of physical memory on that particular
generation. The offending patch causes a regression on TrimSlice, which
is a Tegra20-based device and has a PCI network interface card.

An initial, simpler fix was to change the MSI target address for Tegra20
only, but it was pointed out that the offending commit also prevents the
use of 32-bit only MSI capable devices, even on later chips. Technically
this was never guaranteed to work with the prior code in the first place
because the allocated page could have resided beyond the 4 GiB boundary,
but it is still possible that this could've introduced a regression.

The proper fix that was settled on is to select a fixed address within
the lowest 32 bits of physical address space that is otherwise unused,
but testing of that patch has provided mixed results that are not fully
understood yet.

Given all of the above and the relative urgency to get this fixed in
v4.13, revert the offending commit until a universal fix is found.

Fixes: d7bd554f ("PCI: tegra: Do not allocate MSI target memory")
Reported-by: NTomasz Maciej Nowak <tmn505@gmail.com>
Reported-by: NErik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org	# 4.13.x

Now that we have a custom printf format specifier, convert users of
full_name() to use %pOF instead.  This is preparation for removing storing
of the full path string for each node.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NTyrel Datwyler <tyreld@linux.vnet.ibm.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>

Commit a53e35db ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls to
explicitly state whether the driver needs exclusive or shared reset control
behavior. Convert all drivers requesting exclusive resets to the explicit
API call so the temporary transition helpers can be removed.

No functional changes.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>

The PCI host bridge found on Tegra SoCs doesn't require the MSI target
address to be backed by physical system memory.  Writes are intercepted
within the controller and never make it to the memory pointed to.

Since no actual system memory is required, remove the allocation of a
single page and hardcode the MSI target address with a special address that
maps to the last 4 KiB page within the range that is reserved for system
memory and memory-mapped I/O in the FPCI address map.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

The MSI target address can reside beyond the 32-bit boundary on devices
with more than 2 GiB of system memory.  The PCI host bridge on Tegra can
easily support 64-bit addresses, so make sure to pass the upper 32 bits of
the target address to endpoints when allocating MSI entries.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation

Drop pci_fixup_irqs() usage from PCI tegra host bridge driver.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>

With the introduction of pci_scan_root_bus_bridge() there is no need to
export pci_register_host_bridge() to other kernel subsystems other than the
PCI compilation unit that needs it.

Make pci_register_host_bridge() static to its compilation unit and convert
the existing drivers usage over to pci_scan_root_bus_bridge().
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>

When probing the PCI host controller driver, if an error occurs, the probe
function code does not free memory allocated for the struct pci_host_bridge
resulting in memory leakage.

Move the struct pci_host_bridge allocation over to the respective devm
interface to fix the issue.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>

PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use correct memory mapping attributes to map config space
regions to enforce configuration space non-posted writes behaviour.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>

The PCIe host controller found on Tegra X1 is very similar to its
predecessor on Tegra K1. A bug was introduced in the new revision that
is worked around by always enabling the performance counter, otherwise
accesses to configuration space will block for a number of seconds.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <helgaas@kernel.org>

Tegra210's PCIe controller has a bug that requires the PCA (performance
counter) feature to be enabled. If this isn't done, accesses to device
configuration space will hang the chip for tens of seconds. Implement the
workaround.

Based on commit 514e19138af2 ("pci: tegra: implement PCA enable
workaround") from U-Boot by Stephen Warren <swarren@nvidia.com>.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <helgaas@kernel.org>

Tegra is one of the remaining platforms that still use the traditional
pci_common_init_dev() interface for probing PCI host bridges.

This demonstrates how to convert it to the pci_register_host interface I
just added in a previous patch. This leads to a more linear probe sequence
that can handle errors better because we avoid callbacks into the driver,
and it makes the driver architecture independent.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <helgaas@kernel.org>

The tegra driver never uses the platform drvdata pointer, so don't
bother setting it.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The tegra_pcie_phy_disable() path called pads_writel() with arguments in
the wrong order.  Swap them to be the "value, offset" order expected by
pads_writel().

Fixes: 6fe7c187 ("PCI: tegra: Support per-lane PHYs")
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NThierry Reding <treding@nvidia.com>
CC: stable@vger.kernel.org	# v4.7+

On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped
IO, by reserving a chunk of virtual address space starting at PCI_IOBASE
and by mapping the PCI host bridges memory address space driving PCI IO
cycles to it.

PCI host bridge drivers that enable downstream PCI IO cycles map the host
bridge memory address responding to PCI IO cycles to the fixed virtual
address space through the pci_remap_iospace() API.

This means that if the pci_remap_iospace() function fails, the
corresponding host bridge PCI IO resource must be considered invalid, in
that there is no way for the kernel to actually drive PCI IO transactions
if the memory addresses responding to PCI IO cycles cannot be mapped into
the CPU virtual address space.

The PCI tegra host bridge driver adds the PCI IO resource retrieved from
firmware to the host bridge resource windows even if the
pci_remap_iospace() call fails; this is an actual bug in that the PCI host
bridge would consider the PCI IO resource valid (and possibly assign it to
downstream devices) even if the kernel was not able to map the PCI host
bridge memory address driving IO cycle to the CPU virtual address space (ie
pci_remap_iospace() failures).

Add the PCI host bridge driver pci_remap_iospace() failure path and do not
add the corresponding PCI host bridge PCI IO resources retrieved through
firmware when the pci_remap_iospace() function call fails, fixing the
issue.

Fixes: e6e9f471 ("PCI: tegra: Use generic pci_remap_iospace() rather than ARM32-specific one")
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Thierry Reding <treding@nvidia.com>

of_device_get_match_data() was added in v4.2 to reduce the the boilerplate
required to get at SoC-specific data.  Use it to simplify the code
slightly.

[bhelgaas: changelog]
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The struct tegra_pcie_soc_data represents SoC-specific data.  The shorter
name tegra_pcie_soc already describes that accurately enough, so the extra
five characters are redundant.  Also remove the suffix from various
variable names to shorten the code a little.

This also makes this driver more consistent with the naming used in other
drivers that use a similar mechanism to differentiate between various SoC
generations.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

This code is not being built as a module by anyone:

  drivers/pci/host/Kconfig:config PCI_TEGRA
  drivers/pci/host/Kconfig:       bool "NVIDIA Tegra PCIe controller"

Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.

Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.

Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

[bhelgaas: changelog]
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-tegra@vger.kernel.org

The value that should be programmed into the PADS_REFCLK register varies
per SoC.  Fix the Tegra PCIe driver to program the correct values.  Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The ASIC team has validated all these values, except for the Tegra20 value
which is simply left unchanged in this patch.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NThierry Reding <treding@nvidia.com>

tegra_pcie_phy_power_on() calls tegra_pcie_phy_enable() only for legacy
SoCs.  However, part of tegra_pcie_phy_enable() needs to happen in all
cases.  Move that code up one level into tegra_pcie_phy_power_on().

[bhelgaas: changelog]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

pcibios_min_mem only exists on 32-bit ARM, so using it in pci-tegra.c
prevents the driver from being used on other arches.

In __pci_assign_resource(), we clip the available area based on
PCIBIOS_MIN_MEM.  On 32-bit ARM, this is pcibios_min_mem, with a default
value of 0x01000000.  For Tegra, we discover the space available for PCI
resource allocation from the device tree, and the lowest address that will
ever be available is 0x12000000 (on Tegra124).

The Tegra windows are always higher than the default pcibios_min_mem, so
the __pci_assign_resource() has no effect, so there's no need to adjust
pcibios_min_mem here.

[bhelgaas: changelog]
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Use the pci_remap_iospace() function provided by the PCI core, rather
than the 32-bit ARM-specific pci_ioremap_io().
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Most of the register definitions use lowercase hexadecimal values, with a
few exceptions using uppercase.  Convert the latter to be more in line with
the former.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Use devm_request_pci_bus_resources() to request host bridge window
resources instead of doing it by hand in the driver.

No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

41534e53 ("PCI: tegra: Implement a proper resource hierarchy") did two
things:

  1) It added a top-level resource that encloses all resources declared in
     the DT description, including registers and bridge apertures, and

  2) It requested the bridge apertures, which means the PCI core can track
     the resources used by PCI devices below the bridge.

The latter is necessary, but the former is questionable because there's no
guarantee that the bridge registers and the apertures are contiguous.  In
this example:

  # cat /proc/iomem
  00000000-3fffffff : /pcie-controller@00003000
    00000000-00000fff : /pcie-controller@00003000/pci@1,0
    00003000-000037ff : pads
    00003800-000039ff : afi
    10000000-1fffffff : cs

the resource tree claims that [mem 0x00003a00-0x0fffffff] is consumed by
/pcie-controller@00003000, but it's not mentioned in the DT, and it might
actually be used by other devices.

Remove the top-level resource so we don't claim more than the device
actually consumes.

This reintroduces the problem that we can't match the resources, e.g.,
"pads", "afi", "cs", etc., to the DT device.  I think this should be solved
by having the DT core request all resources of all devices in the DT (it
does not do that today).  If a driver claims the device, it can request the
resources it uses.  For example:

  # cat /proc/iomem
  00000000-00000fff : /pcie-controller@00003000
    00000000-00000fff : /pcie-controller@00003000/pci@1,0
  00003000-000037ff : /pcie-controller@00003000
    00003000-000037ff : pads
  00003800-000039ff : /pcie-controller@00003000
    00003800-000039ff : afi
  10000000-1fffffff : /pcie-controller@00003000
    10000000-1fffffff : cs
  ...
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The current XUSB pad controller bindings are insufficient to describe
PHY devices attached to USB controllers. New bindings have been created
to overcome these restrictions. As a side-effect each root port now is
assigned a set of PHY devices, one for each lane associated with the
root port. This has the benefit of allowing fine-grained control of the
power management for each lane.
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

BARs are disabled when the size register is 0, so it's misleading to write
a base address into the start register.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Track the offsets of the bus -> CPU mapping for I/O and memory.  This is
cosmetic for current Tegra chips because the offset is always 0.  But to
properly support legacy use-cases, like VGA, this would be needed so that
PCI bus addresses can be relocated.

While at it, also request the I/O resource both in physical memory and I/O
space to make /proc/iomem consistent, as well as add the I/O region to the
list of host bridge resources.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>