1. 28 7月, 2009 1 次提交
    • B
      mm: Pass virtual address to [__]p{te,ud,md}_free_tlb() · 9e1b32ca
      Benjamin Herrenschmidt 提交于
      mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()
      
      Upcoming paches to support the new 64-bit "BookE" powerpc architecture
      will need to have the virtual address corresponding to PTE page when
      freeing it, due to the way the HW table walker works.
      
      Basically, the TLB can be loaded with "large" pages that cover the whole
      virtual space (well, sort-of, half of it actually) represented by a PTE
      page, and which contain an "indirect" bit indicating that this TLB entry
      RPN points to an array of PTEs from which the TLB can then create direct
      entries. Thus, in order to invalidate those when PTE pages are deleted,
      we need the virtual address to pass to tlbilx or tlbivax instructions.
      
      The old trick of sticking it somewhere in the PTE page struct page sucks
      too much, the address is almost readily available in all call sites and
      almost everybody implemets these as macros, so we may as well add the
      argument everywhere. I added it to the pmd and pud variants for consistency.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: David Howells <dhowells@redhat.com> [MN10300 & FRV]
      Acked-by: NNick Piggin <npiggin@suse.de>
      Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [s390]
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      9e1b32ca
  2. 23 7月, 2009 1 次提交
  3. 21 7月, 2009 1 次提交
  4. 19 7月, 2009 1 次提交
  5. 18 7月, 2009 1 次提交
    • T
      vmlinux.lds.h: restructure BSS linker script macros · 04e448d9
      Tim Abbott 提交于
      The BSS section macros in vmlinux.lds.h currently place the .sbss
      input section outside the bounds of [__bss_start, __bss_end].  On all
      architectures except for microblaze that handle both .sbss and
      __bss_start/__bss_end, this is wrong: the .sbss input section is
      within the range [__bss_start, __bss_end].  Relatedly, the example
      code at the top of the file actually has __bss_start/__bss_end defined
      twice; I believe the right fix here is to define them in the
      BSS_SECTION macro but not in the BSS macro.
      
      Another problem with the current macros is that several
      architectures have an ALIGN(4) or some other small number just before
      __bss_stop in their linker scripts.  The BSS_SECTION macro currently
      hardcodes this to 4; while it should really be an argument.  It also
      ignores its sbss_align argument; fix that.
      
      mn10300 is the only user at present of any of the macros touched by
      this patch.  It looks like mn10300 actually was incorrectly converted
      to use the new BSS() macro (the alignment of 4 prior to conversion was
      a __bss_stop alignment, but the argument to the BSS macro is a start
      alignment).  So fix this as well.
      
      I'd like acks from Sam and David on this one.  Also CCing Paul, since
      he has a patch from me which will need to be updated to use
      BSS_SECTION(0, PAGE_SIZE, 4) once this gets merged.
      Signed-off-by: NTim Abbott <tabbott@ksplice.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: David Howells <dhowells@redhat.com>
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      04e448d9
  6. 17 7月, 2009 7 次提交
  7. 16 7月, 2009 20 次提交
  8. 15 7月, 2009 2 次提交
  9. 14 7月, 2009 2 次提交
  10. 13 7月, 2009 4 次提交
    • R
      x86, apic: Fix false positive section mismatch in numaq_32.c · 7473727b
      Rakib Mullick 提交于
      The variable apic_numaq placed in noninit section references the
      function wakeup_secondary_cpu_via_nmi(), which is in __cpuinit
      section. Thus causes a section mismatch warning. To avoid such
      mismatch we mark apic_numaq as __refdata.
      
      We were warned by the following warning:
      
        WARNING: arch/x86/kernel/built-in.o(.data+0x932c): Section mismatch in
        reference from the variable apic_numaq to the function
        .cpuinit.text:wakeup_secondary_cpu_via_nmi()
      Signed-off-by: NRakib Mullick <rakib.mullick@gmail.com>
      LKML-Reference: <b9df5fa10907120407p6b4f67dtf4d563155488188a@mail.gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7473727b
    • R
      x86: Fix false positive section mismatch in es7000_32.c · 151586d0
      Rakib Mullick 提交于
      The variable apic_es7000_cluster references the function __cpuinit
      wakeup_secondary_cpu_via_mip() from a noninit section. So we've been
      warned by the following warning. To avoid possible collision between
      init/noninit, its best to mark the variable as __refdata.
      
      We were warned by the following warning:
      
        LD      arch/x86/kernel/apic/built-in.o
        WARNING: arch/x86/kernel/apic/built-in.o(.data+0x198c): Section
        mismatch in reference from the variable apic_es7000_cluster to the
        function .cpuinit.text:wakeup_secondary_cpu_via_mip()
      Signed-off-by: NRakib Mullick <rakib.mullick@gmail.com>
      LKML-Reference: <b9df5fa10907120404k6279a10ch5e9682432272706f@mail.gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      151586d0
    • D
      perf_counter, x86: Extend perf_counter Pentium M support · f1c6a581
      Daniel Qarras 提交于
      I've attached a patch to remove the Pentium M special casing of
      EMON and as noticed at least with my Pentium M the hardware PMU
      now works:
      
       Performance counter stats for '/bin/ls /var/tmp':
      
             1.809988  task-clock-msecs         #      0.125 CPUs
                    1  context-switches         #      0.001 M/sec
                    0  CPU-migrations           #	 0.000 M/sec
                  224  page-faults              #	 0.124 M/sec
              1425648  cycles                   #    787.656 M/sec
               912755  instructions             #	 0.640 IPC
      
      Vince suggested that this code was trying to address erratum
      Y17 in Pentium-M's:
      
        http://download.intel.com/support/processors/mobile/pm/sb/25266532.pdf
      
      But that erratum (related to IA32_MISC_ENABLES.7) does not
      affect perfcounters as we dont use this toggle to disable RDPMC
      and WRMSR/RDMSR access to performance counters. We keep cr4's
      bit 8 (X86_CR4_PCE) clear so unprivileged RDPMC access is not
      allowed anyway.
      
      Cc: Vince Weaver <vince@deater.net>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Stephane Eranian <eranian@googlemail.com>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f1c6a581
    • K
      sparc: remove driver-core BUS_ID_SIZE · 08f42877
      Kay Sievers 提交于
      The name size limit is gone from the driver-core, the BUS_ID_SIZE
      value will be removed.
      
      Cc: David S. Miller <davem@davemloft.net>
      Signed-off-by: NKay Sievers <kay.sievers@vrfy.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      08f42877