This adds dpm support for rs780/rs880 asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic voltage scaling

set radeon.dpm=1 to enable it.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Has a different dpm controller than r600.

v2: rebase on gpu reset changes
v3: rebase on get_xclk changes
v4: update rptr/wtpr callbacks
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: fix up for latest reset changes
v3: use CP for pt updates for now
v4: update for 2 level PTs
v5: update for ib_parse removal
v6: vm_flush api change
v7: rebase
v8: fix gfx ring function pointers
v9: fix vm_set_page function params
v10: update for compute changes
v11: cleanup for release
v12: update rptr/wptr callbacks
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add callbacks to the radeon_asic struct to handle
rptr/wptr fetchs and wptr updates.
We currently use one version for all rings, but this
allows us to override with a ring specific versions.

Needed for compute rings on CIK.

v2: udpate as per Christian's comments
v3: fix some rebase cruft
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: fix trailing whitespace
Signed-off-by: NSamuel Li <samuel.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Register audio callbacks for asic where we support
audio.  Cleans up the code and makes it easier to
add support for newer asics.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Uses the same functions as older asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: avoid 64bit divide
v3: rv740 uses the evegreen upll configuration
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>

Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: remove unneeded register definitions
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: write clk registers only once!
v3: update cg scratch register properly
v4: add TN support
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Just everything needed to decode videos using UVD.

v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
    add support for HEMLOCK, add buffer sizes checks
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Cleans up the code for future asics

v2: rebase, fix some missing radeon_asic updates
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This is required to get the reference clock used
by the gfx engine for things like timestamps. Fixes
support for GL extensions the use timestamps on
certain boards.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Now that we have switched to using IBs for page table updates,
we can switch back the using the DMA ring.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

fetch the reset mask and check if the relevant ring flags
are set to determine whether the ring is hung or not.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For large VM page table updates, we can sometimes generate
more packets than there is space on the ring.  This happens
more readily with the DMA ring since it is 64K (vs 1M for the
CP).  For now, switch back to the CP.  For the next kernel,
I have a patch to utilize IBs for VM PT updates which
alleviates this problem.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=58354Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- r6xx actually uses a slightly different packet format,
although both formats seem to work ok.
- r7xx doesn't have the count multiple of 2 limitation.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows us to use async DMA from userspace.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows us to use the DMA ring from userspace.
DMA doesn't have a good NOP packet in which to embed the
reloc idx, so userspace has to add a reloc for each
buffer used and order them to match the command stream.

v2: fix address bounds checking
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows us to use the DMA ring from userspace.
DMA doesn't have a good NOP packet in which to embed the
reloc idx, so userspace has to add a reloc for each
buffer used and order them to match the command stream.

v2: fix address bounds checking, reloc indexing
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DMA engine has special packets to facilitate this and it also keeps
the 3D engine free for other things.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DMA engine has special packets to facilitate this and it also keeps
the 3D engine free for other things.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Pretty much the same as cayman.  Some changes to the copy
packets.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There are 2 async DMA engines on cayman, one at 0xd000 and
one at 0xd800.  The programming interface is the same as
evergreen however there are some changes to the commands
for using vmids.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Pretty similar to 6xx/7xx except the count field increased in the
packet header and the max IB size increased.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Uses the new multi-ring infrastucture.  6xx/7xx has a single
async DMA ring.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use the new WRITE_DATA packet rather than the legacy
ME_WRITE packet.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Starting on BTC, there are no longer separate states for
single head and multi-head, we just use the high mclk/voltage
for all states for multi-head.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=49981

v2: fix typo
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Read back the backlight level from the hw.
Needed for proper backlight restoration on resume.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Currently doing the update with the CP.

v2: Rebased on Jeromes bugfix. Make validity comparison
    more human readable.
Signed-off-by: NChristian König <deathsimple@vodafone.de>

Makes it easier to move it into the rings.
Signed-off-by: NChristian König <deathsimple@vodafone.de>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>

Move binding onto the ring, simplifying handling a bit.
Signed-off-by: NChristian König <deathsimple@vodafone.de>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>