1. 08 11月, 2005 6 次提交
  2. 07 11月, 2005 5 次提交
  3. 31 10月, 2005 2 次提交
  4. 30 10月, 2005 1 次提交
  5. 15 10月, 2005 1 次提交
    • D
      [SPARC64]: Fix powering off on SMP. · b4d1b825
      David S. Miller 提交于
      Doing a "SUNW,stop-self" firmware call on the other cpus is not the
      correct thing to do when dropping into the firmware for a halt,
      reboot, or power-off.
      
      For now, just do nothing to quiet the other cpus, as the system should
      be quiescent enough.  Later we may decide to implement smp_send_stop()
      like the other SMP platforms do.
      
      Based upon a report from Christopher Zimmermann.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b4d1b825
  6. 14 10月, 2005 2 次提交
  7. 13 10月, 2005 1 次提交
    • D
      [SPARC64]: Fix boot failures on SunBlade-150 · c9c10830
      David S. Miller 提交于
      The sequence to move over to the Linux trap tables from
      the firmware ones needs to be more air tight.  It turns
      out that to be %100 safe we do need to be able to translate
      OBP mappings in our TLB miss handlers early.
      
      In order not to eat up a lot of kernel image memory with
      static page tables, just use the translations array in
      the OBP TLB miss handlers.  That solves the bulk of the
      problem.
      
      Furthermore, to make sure the OBP TLB miss path will work
      even before the fixed MMU globals are loaded, explicitly
      load %g1 to TLB_SFSR at the beginning of the i-TLB and
      d-TLB miss handlers.
      
      To ease the OBP TLB miss walking of the prom_trans[] array,
      we sort it then delete all of the non-OBP entries in there
      (for example, there are entries for the kernel image itself
      which we're not interested in at all).
      
      We also save about 32K of kernel image size with this change.
      Not a bad side effect :-)
      
      There are still some reasons why trampoline.S can't use the
      setup_trap_table() yet.  The most noteworthy are:
      
      1) OBP boots secondary processors with non-bias'd stack for
         some reason.  This is easily fixed by using a small bootup
         stack in the kernel image explicitly for this purpose.
      
      2) Doing a firmware call via the normal C call prom_set_trap_table()
         goes through the whole OBP enter/exit sequence that saves and
         restores OBP and Linux kernel state in the MMUs.  This path
         unfortunately does a "flush %g6" while loading up the OBP locked
         TLB entries for the firmware call.
      
         If we setup the %g6 in the trampoline.S code properly, that
         is in the PAGE_OFFSET linear mapping, but we're not on the
         kernel trap table yet so those addresses won't translate properly.
      
         One idea is to do a by-hand firmware call like we do in the
         early bootup code and elsewhere here in trampoline.S  But this
         fails as well, as aparently the secondary processors are not
         booted with OBP's special locked TLB entries loaded.  These
         are necessary for the firwmare to processes TLB misses correctly
         up until the point where we take over the trap table.
      
      This does need to be resolved at some point.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c9c10830
  8. 12 10月, 2005 1 次提交
    • D
      [SPARC64]: Fix net booting on Ultra5 · b1b510aa
      David S. Miller 提交于
      We were not doing alignment properly when remapping the kernel image.
      
      What we want is a 4MB aligned physical address to map at KERNBASE.
      Mistakedly we were 4MB aligning the virtual address where the kernel
      initially sits, that's wrong.
      
      Instead, we should PAGE align the virtual address, then 4MB align the
      physical address result the prom gives to us.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b1b510aa
  9. 11 10月, 2005 1 次提交
    • D
      [SPARC64]: Fix Ultra5, Ultra60, et al. boot failures. · 5d8e1b18
      David S. Miller 提交于
      On the boot processor, we need to do the move onto the Linux trap
      table a little bit differently else we'll take unhandlable faults in
      the firmware address space.
      
      Previously we would do the following:
      
      1) Disable PSTATE_IE in %pstate.
      2) Set %tba by hand to sparc64_ttable_tl0
      3) Initialize alternate, mmu, and interrupt global
         trap registers.
      4) Call prom_set_traptable()
      
      That doesn't work very well actually with the way we boot the kernel
      VM these days.  It worked by luck on many systems because the firmware
      accesses for the prom_set_traptable() call happened to be loaded into
      the TLB already, something we cannot assume.
      
      So the new scheme is this:
      
      1) Clear PSTATE_IE in %pstate and set %pil to 15
      2) Call prom_set_traptable()
      3) Initialize alternate, mmu, and interrupt global
         trap registers.
      
      and this works quite well.  This sequence has been moved into a
      callable function in assembler named setup-trap_table().  The idea is
      that eventually trampoline.S can use this code as well.  That isn't
      possible currently due to some complications, but eventually we should
      be able to do it.
      
      Thanks to Meelis Roos for the Ultra5 boot failure report.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5d8e1b18
  10. 09 10月, 2005 1 次提交
  11. 08 10月, 2005 1 次提交
  12. 07 10月, 2005 1 次提交
  13. 05 10月, 2005 1 次提交
  14. 30 9月, 2005 2 次提交
  15. 29 9月, 2005 7 次提交
  16. 28 9月, 2005 1 次提交
  17. 26 9月, 2005 2 次提交
    • D
      [SPARC64]: Probe D/I/E-cache config and use. · 80dc0d6b
      David S. Miller 提交于
      At boot time, determine the D-cache, I-cache and E-cache size and
      line-size.  Use them in cache flushes when appropriate.
      
      This change was motivated by discovering that the D-cache on
      UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
      Cheetah error handlers were assuming a 32K size.
      
      There are still some pieces of code that are hard coding things and
      will need to be fixed up at some point.
      
      While we're here, fix the D-cache and I-cache parity error handlers
      to run with interrupts disabled, and when the trap occurs at trap
      level > 1 log the event via a counter displayed in /proc/cpuinfo.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      80dc0d6b
    • D
      [SPARC64]: Add CONFIG_DEBUG_PAGEALLOC support. · 56425306
      David S. Miller 提交于
      The trick is that we do the kernel linear mapping TLB miss starting
      with an instruction sequence like this:
      
      	ba,pt		%xcc, kvmap_load
      	 xor		%g2, %g4, %g5
      
      succeeded by an instruction sequence which performs a full page table
      walk starting at swapper_pg_dir.
      
      We first take over the trap table from the firmware.  Then, using this
      constant PTE generation for the linear mapping area above, we build
      the kernel page tables for the linear mapping.
      
      After this is setup, we patch that branch above into a "nop", which
      will cause TLB misses to fall through to the full page table walk.
      
      With this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      56425306
  18. 25 9月, 2005 1 次提交
  19. 24 9月, 2005 1 次提交
  20. 23 9月, 2005 2 次提交
    • D
      [SPARC64]: Fix comment typo in head.S · a8201c61
      David S. Miller 提交于
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a8201c61
    • D
      [SPARC64]: Rewrite bootup sequence. · bff06d55
      David S. Miller 提交于
      Instead of all of this cpu-specific code to remap the kernel
      to the correct location, use portable firmware calls to do
      this instead.
      
      What we do now is the following in position independant
      assembler:
      
      	chosen_node = prom_finddevice("/chosen");
      	prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
      	vaddr = 4MB_ALIGN(current_text_addr());
      	prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
      	prom_boot_mapping_mode = mode;
      	prom_boot_mapping_phys_high = paddr_high;
      	prom_boot_mapping_phys_low = paddr_low;
      	prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
      
      and that replaces the massive amount of by-hand TLB probing and
      programming we used to do here.
      
      The new code should also handle properly the case where the kernel
      is mapped at the correct address already (think: future kexec
      support).
      
      Consequently, the bulk of remap_kernel() dies as does the entirety
      of arch/sparc64/prom/map.S
      
      We try to share some strings in the PROM library with the ones used
      at bootup, and while we're here mark input strings to oplib.h routines
      with "const" when appropriate.
      
      There are many more simplifications now possible.  For one thing, we
      can consolidate the two copies we now have of a lot of cpu setup code
      sitting in head.S and trampoline.S.
      
      This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bff06d55