The majority of changes are necessary to remove dependencies on header
files within arch/arm/mach-zynq/include/mach:

  uncompress.h
    - Deleted. It is unused for ARCH_MULTIPLATFORM builds.

  uart.h:
    - Move uart definitions out of uart.h into debug/zynq.S, which is
      now the only user

  zynq_soc.h:
    - Move SCU address definitions into common.c.
    - Other #defines, such as PERIPHERAL_CLOCK_RATE, TTC0_BASE, etc, are
      unused and can be dropped
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

Convert low-level debugging routines to make use of debug_ll_io_init().
This is part of the preparation for ARCH_MULTIPLATFORM support for Zynq.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

Now that the TTC driver has proper support for DT bindings, it is not
necessary for the registers to be mapped early.  They will be mapped
during clock initialization using of_iomap().  Remove the early mapping.

In addition, remove the extraneous zynq_soc.h include from the timer
driver.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

Make the Zynq platform use the newly created zynq clk bindings.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The purpose of the created zynq-7000.dtsi file is to describe the
hardware common to all Zynq 7000-based boards.  Also, get rid of the
zynq-ep107 device tree, since it is not hardware anyone can purchase.

Add a zc702 dts file based on the zynq-7000.dtsi.  Add it to the
dts/Makefile so it is built with the 'dtbs' target.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The main UART on the Xilinx ZC702 board is UART1, located at address
e0001000.  Add a Kconfig option to select this device as the low-level
debugging port.  This allows the really early boot printouts to reach
the USB serial adaptor on this board.

For consistency's sake, add a choice entry for UART0 even though it is
the the default if UART1 is not selected.
Signed-off-by: NNick Bowler <nbowler@elliptictech.com>
Tested-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Move the sys_timer definition out of ttc driver and make it part of the
common zynq code.  This is preparation for renaming and COMMON_CLK
support.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

Shifting them up into the vmalloc region prevents the following warning,
when booting a zynq qemu target with more than 512mb of RAM:

  BUG: mapping for 0xe0000000 at 0xe0000000 out of vmalloc space

In addition, it allows for reuse of these mappings when the proper
drivers issue requests via ioremap().

There are currently unknown issues with the early uart mapping.  For
now, the uart will be mapped to a known working address.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq support in mainline does not (yet) make use of any of the
generic clk or clk lookup functionality.  Remove what is upstream for
now, until the out-of-tree implementation is in suitable form for
merging.

An important side effect of this patch is that it allows the building of
a Zynq kernel without running into unresolved symbol problems:

   drivers/built-in.o: In function `amba_get_enable_pclk':
   clkdev.c:(.text+0x444): undefined reference to `clk_enable'
   drivers/built-in.o: In function `amba_remove':
   clkdev.c:(.text+0x488): undefined reference to `clk_disable'
   drivers/built-in.o: In function `amba_probe':
   clkdev.c:(.text+0x540): undefined reference to `clk_disable'
   drivers/built-in.o: In function `amba_device_add':
   clkdev.c:(.text+0x77c): undefined reference to `clk_disable'
   drivers/built-in.o: In function `enable_clock':
   clkdev.c:(.text+0x29738): undefined reference to `clk_enable'
   drivers/built-in.o: In function `disable_clock':
   clkdev.c:(.text+0x29778): undefined reference to `clk_disable'
   drivers/built-in.o: In function `__pm_clk_remove':
   clkdev.c:(.text+0x297f8): undefined reference to `clk_disable'
   drivers/built-in.o: In function `pm_clk_suspend':
   clkdev.c:(.text+0x29bc8): undefined reference to `clk_disable'
   drivers/built-in.o: In function `pm_clk_resume':
   clkdev.c:(.text+0x29c28): undefined reference to `clk_enable'
   make[2]: *** [vmlinux] Error 1
   make[1]: *** [sub-make] Error 2
   make: *** [all] Error 2

In addition, eliminate Zynq's "use" of the versatile platform, as it is
no longer needed.  As Nick Bowler points out:

   For the record, I think this was introduced by commit 56a34b03
   ("ARM: versatile: Make plat-versatile clock optional") which forgot to
   select PLAT_VERSATILE_CLOCK on Zynq.  This is not all that surprising,
   because the fact that Zynq "uses" PLAT_VERSATILE is secretly hidden in
   the Makefile.

   Nevertheless, the only feature from versatile that Zynq needed was the
   clock support, so this patch should *also* delete the secret use of
   plat-versatile by removing this line from arch/arm/Makefile:

      plat-$(CONFIG_ARCH_ZYNQ)      += versatile
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq has a PL310 L2 cache controller.  Convert in-tree uses to using
the device tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq uses the cortex-a9-gic.  This eliminates the need to hardcode
register addresses.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

Convert the zynq platform to be using the gic_handle_irq
function as its primary interrupt handler.
Acked-by: NJohn Linn <john.linn@xilinx.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The zynq platform will never have board files other than the
device tree one, so there is no point splitting it from common.c.

This makes the code more compact.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJohn Linn <john.linn@xilinx.com>

The 1st board support is minimal to get a system up and running
on the Xilinx platform.

This platform reuses the clock implementation from plat-versatile, and
it depends entirely on CONFIG_OF support.  There is only one board
support file which obtains all device information from a device tree
dtb file which is passed to the kernel at boot time.
Signed-off-by: NJohn Linn <john.linn@xilinx.com>