1. 29 9月, 2012 1 次提交
  2. 07 7月, 2012 2 次提交
  3. 27 3月, 2012 1 次提交
    • M
      mtd: nand: add support for diskonchip G4 nand flash device · 570469f3
      Mike Dunn 提交于
      This patch adds a driver for the M-Sys / Sandisk diskonchip G4 nand flash found
      in various smartphones and PDAs, among them the Palm Treo680, HTC Prophet and
      Wizard, Toshiba Portege G900, Asus P526, and O2 XDA Zinc.  It was tested on the
      Treo 680, but should work generically.
      
      Since v3, this patch adds power management functions, a scan of the factory bad
      block table during initialization, several fixes, and more extensive testing.
      Also, the platform data header file, which only contained partitioning
      information, was removed.  Command-line partitioning can be used, at least until
      an mtd parser is written for the saftl format with which these chips are
      shipped.
      Signed-off-by: NMike Dunn <mikedunn@newsguy.com>
      Reviewed-by: NRobert Jarzmik <robert.jarzmik@free.fr>
      Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      570469f3
  4. 16 3月, 2012 1 次提交
  5. 11 9月, 2011 2 次提交
  6. 12 3月, 2011 1 次提交
    • I
      mtd: nand: add software BCH ECC support · 193bd400
      Ivan Djelic 提交于
      This patch adds software BCH ECC support to mtd, in order to handle recent
      NAND device ecc requirements (4 bits or more).
      
      It does so by adding a new ecc mode (NAND_ECC_SOFT_BCH) for use by board
      drivers, and a new Kconfig option to enable BCH support. It relies on the
      generic BCH library introduced in a previous patch.
      
      When a board driver uses mode NAND_ECC_SOFT_BCH, it should also set fields
      chip->ecc.size and chip->ecc.bytes to select BCH ecc data size and required
      error correction capability. See nand_bch_init() documentation for details.
      
      It has been tested on the following platforms using mtd-utils, UBI and
      UBIFS: x86 (with nandsim), arm926ejs.
      Signed-off-by: NIvan Djelic <ivan.djelic@parrot.com>
      Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      193bd400
  7. 25 10月, 2010 1 次提交
  8. 05 8月, 2010 1 次提交
  9. 13 5月, 2010 1 次提交
  10. 26 3月, 2010 1 次提交
  11. 27 2月, 2010 3 次提交
  12. 06 1月, 2010 1 次提交
  13. 01 1月, 2010 1 次提交
  14. 17 12月, 2009 1 次提交
  15. 20 10月, 2009 1 次提交
  16. 20 9月, 2009 2 次提交
  17. 06 6月, 2009 1 次提交
  18. 06 4月, 2009 1 次提交
  19. 21 3月, 2009 1 次提交
  20. 20 3月, 2009 1 次提交
  21. 18 10月, 2008 1 次提交
  22. 14 10月, 2008 1 次提交
  23. 03 9月, 2008 1 次提交
  24. 11 8月, 2008 1 次提交
  25. 04 8月, 2008 1 次提交
  26. 07 6月, 2008 1 次提交
  27. 05 6月, 2008 1 次提交
  28. 23 4月, 2008 2 次提交
    • A
      [MTD] [NAND] FSL UPM NAND driver · 5c249c5a
      Anton Vorontsov 提交于
      This is very simple driver, NAND is connected through localbus,
      and User-Programmable Machine is doing various adjustments to
      speak NAND. No special efforts needed to do read and write cycles,
      though to control ALE and CLE phases, we ask UPM to generate exact
      pre-programmed signals on the localbus lines.
      Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      5c249c5a
    • E
      [MTD] [NAND] support for pxa3xx · fe69af00
      eric miao 提交于
      This is preliminary since:
      
      1. It supports only _one_ chip select at the moment. As there is no
         existing platforms available using two chip selects of the NAND
         controller, it shall really not include code for supporting the
         2nd chip select for now, as such code cannot be verified.
      
      2. It resorts to the default and simpliest memory based badblock
         table
      
      3. Only limited types of nand flash are currently supported. Most
         PXA3xx processors come with on-chip NAND flash dies, so there
         isn't much flexibility for other types of NAND.
      
      4. The NAND controller should be configured to detect the device's
         ID, thus making it difficult to use nand_scan_ident() to assist
         the detection process (though it's not impossible)
      
      TODO: fix all the above limitations of cuz :-)
      Signed-off-by: Neric miao <eric.miao@marvell.com>
      Cc: Sergey Podstavin <spodstavin@ru.mvista.com>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      fe69af00
  29. 07 2月, 2008 1 次提交
  30. 03 12月, 2007 1 次提交
  31. 29 11月, 2007 1 次提交
  32. 13 10月, 2007 1 次提交
    • B
      [MTD] [NAND] Blackfin on-chip NAND Flash Controller driver · b37bde14
      Bryan Wu 提交于
      This is the driver for latest Blackfin on-chip nand flash controller
      
       - use nand_chip and mtd_info common nand driver interface
       - provide both PIO and dma operation
       - compiled with ezkit bf548 configuration
       - use hardware 1-bit ECC
       - tested with YAFFS2 and can mount YAFFS2 filesystem as rootfs
      
      ChangeLog from try#1
       - use hweight32() instead of count_bits()
       - replace bf54x with bf5xx and BF54X with BF5XX
       - compare against plat->page_size in 2 cases when enable hardware ECC
      
      ChangeLog from try#2
       - passed nand_test suites
       - use cpu_relax() instead of busy wait loop
       - some coding style issue pointed out by Andrew
      Signed-off-by: NBryan Wu <bryan.wu@analog.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      b37bde14
  33. 30 8月, 2007 1 次提交
  34. 08 5月, 2007 1 次提交