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  1. 21 10月, 2006 3 次提交
  3. 04 10月, 2006 1 次提交
  5. 22 9月, 2006 1 次提交
  7. 16 9月, 2006 1 次提交
  9. 17 8月, 2006 2 次提交
  11. 15 8月, 2006 1 次提交
  13. 15 7月, 2006 1 次提交
    • A
      [MTD] Fixes of performance and stability issues in CFI driver. · 46a1652c
      由 Alexey Korolev 提交于 
      Fix of performance and stability issues on Intel NOR chips. It fixes:

1. Very low write performance on Sibley (perf tests demonstrated write
   performance less than 100Kb/sec when it should be over 400Kb/sec).

2. Low erase performance. (perf tests on Sibleuy demonstrated erase
   performance 246Kb/sec when it should be over 300Kb/sec).

3. Error on JFFS2 tests with CPU loading application when MTD returns
   "block erase error: (status timeout)" To fix the issue it does the
   following:
     1. Removes the timeout tuning from inval_cache_and_wait_for_operation.
     2. Waiting conditions in inval_cache_and_wait_for_operation now is
         based on timer resolution
        If timeout is lower than timer resolution then we do in cycle
	  "Checking the status"
	  udelay(1);
	  cond_resched();
        If timeout is greater than timer resolution (probably erase
        operation) We do the following
	  sleep for half of operation timeout and do in cycle the following
	    "Checking the status"
	    sleep for timer resolution
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NAlexey Korolev <akorolev@infradead.org>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      46a1652c
  15. 01 7月, 2006 1 次提交
  17. 22 6月, 2006 1 次提交
  19. 15 6月, 2006 1 次提交
  21. 14 6月, 2006 1 次提交
  23. 30 5月, 2006 2 次提交
  25. 23 5月, 2006 3 次提交
    • J
      [MTD] Introduce MTD_BIT_WRITEABLE · 5fa43394
      由 Joern Engel 提交于 
      o Add a flag MTD_BIT_WRITEABLE for devices that allow single bits to be
  cleared.
o Replace MTD_PROGRAM_REGIONS with a cleared MTD_BIT_WRITEABLE flag for
  STMicro and Intel Sibley flashes with internal ECC.  Those flashes
  disallow clearing of single bits, unlike regular NOR flashes, so the
  new flag models their behaviour better.
o Remove MTD_ECC.  After the STMicro/Sibley merge, this flag is only set
  and never checked.
Signed-off-by: NJoern Engel <joern@wh.fh-wedel.de>
      5fa43394
    • J
      [MTD] Merge STMicro NOR_ECC code with Intel Sibley code · c8b229de
      由 Joern Engel 提交于 
      In 2002, STMicro started producing NOR flashes with internal ECC protection
for small blocks (8 or 16 bytes).  Support for those flashes was added by me.
In 2005, Intel Sibley flashes copied this strategy and Nico added support for
those.  Merge the code for both.
Signed-off-by: NJoern Engel <joern@wh.fh-wedel.de>
      c8b229de
    • J
      [MTD] Introduce writesize · 28318776
      由 Joern Engel 提交于 
      At least two flashes exists that have the concept of a minimum write unit,
similar to NAND pages, but no other NAND characteristics.  Therefore, rename
the minimum write unit to "writesize" for all flashes, including NAND.
Signed-off-by: NJoern Engel <joern@wh.fh-wedel.de>
      28318776
  27. 22 5月, 2006 1 次提交
  29. 20 5月, 2006 1 次提交
  31. 18 5月, 2006 1 次提交
  33. 17 5月, 2006 3 次提交
  35. 14 5月, 2006 2 次提交
  37. 09 5月, 2006 2 次提交
  39. 17 4月, 2006 1 次提交
  41. 01 4月, 2006 4 次提交
  43. 27 3月, 2006 1 次提交
  45. 25 2月, 2006 1 次提交
  47. 21 2月, 2006 1 次提交
  49. 08 2月, 2006 1 次提交
  51. 17 1月, 2006 2 次提交