1. 05 2月, 2008 1 次提交
    • D
      intel-agp: add chipset flushing support · 6c00a61e
      Dave Airlie 提交于
      This adds support for flushing the chipsets on the 915, 945, 965 and G33
      families of Intel chips.
      
      The BIOS doesn't seem to always allocate the BAR on the 965 chipsets
      so I have to use pci resource code to create a resource
      
      It adds an export for pcibios_align_resource.
      6c00a61e
  2. 04 2月, 2008 1 次提交
  3. 02 2月, 2008 1 次提交
  4. 30 1月, 2008 4 次提交
    • A
      x86: serverworks: IRQ routing needs no _p · c11b68bc
      Alan Cox 提交于
      I can find no reason for the _p on the serverworks IRQ routing logic, and
      a review of the documentation contains no indication that any such delay
      is needed so lets try this
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      c11b68bc
    • P
      x86: coding style fixes in arch/x86/pci/fixup.c · 938f6671
      Paolo Ciarrocchi 提交于
      Simple coding style fixes.
      
      no code changed:
      
         text    data     bss     dec     hex filename
         3139     576     194    3909     f45 fixup.o.before
         3139     576     194    3909     f45 fixup.o.after
      
        md5:
         9a3467057478b2d99962bdd448282eeb  fixup.o.before.asm
         9a3467057478b2d99962bdd448282eeb  fixup.o.after.asm
      Signed-off-by: NPaolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      938f6671
    • I
      x86: add some pirq debugging · 7d409d60
      Ingo Molnar 提交于
      we use a few static mapping rules in our pirq routing functions,
      and for example regression f3ac8432 was due to the pirq
      being out of range of the remapping array. Put in a few
      WARN_ON_ONCE() lines so that we get notified about any such
      out-of-bound incidents.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      7d409d60
    • G
      PCI: remove default PCI expansion ROM memory allocation · 9f8dacca
      Gary Hade 提交于
      increasing number of PCI slots in large multi-node systems.  The kernel
      currently attempts by default to allocate memory for all PCI expansion
      ROMs so there has also been an increasing number of PCI memory
      allocation failures seen on these systems.  This occurs because the BIOS
      either (1) provides insufficient PCI memory resource for all the
      expansion ROMs or (2) provides adequate PCI memory resource for
      expansion ROMs but provides the space in kernel unexpected BIOS assigned
      P2P non-prefetch windows.
      
      The resulting PCI memory allocation failures may be benign when related
      to memory requests for expansion ROMs themselves but in some cases they
      can occur when attempting to allocate space for more critical BARs.
      This can happen when a successful expansion ROM allocation request
      consumes memory resource that was intended for a non-ROM BAR.  We have
      seen this happen during PCI hotplug of an adapter that contains a P2P
      bridge where successful memory allocation for an expansion ROM BAR on
      device behind the bridge consumed memory that was intended for a non-ROM
      BAR on the P2P bridge.  In all cases the allocation failure messages can
      be very confusing for users.
      
      This patch addresses the issue by changing the kernel default behavior
      so that expansion ROM memory allocations are no longer attempted by
      default when the BIOS has not assigned a specific address range to the
      expansion ROM BAR.  This was done by changing the 'pci=rom' boot option
      behavior for BIOS unassigned expansion ROMs to actually match it's
      current kernel-parameters.txt description which already implies "off" by
      default. Behavior for BIOS assigned expansion ROMs implemented in
      pcibios_assign_resources() [arch/x86/pci/i386.c] is unchanged.
      Signed-off-by: NGary Hade <garyhade@us.ibm.com>
      Cc: Greg KH <greg@kroah.com>
      Cc: Jan Beulich <jbeulich@novell.com>
      Acked-by: N"Jun'ichi Nomura" <j-nomura@ce.jp.nec.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      9f8dacca
  5. 27 11月, 2007 1 次提交
  6. 17 11月, 2007 2 次提交
    • Y
      x86: check boundary in count setup resource · 3d9befd2
      Yinghai Lu 提交于
      need to check info->res_num less than PCI_BUS_NUM_RESOURCES, so
      info->bus->resource[info->res_num] = res will not beyond of bus resource
      array when acpi returns too many resource entries.
      Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
      Cc: Greg Kroah-Hartman <gregkh@suse.de>
      Cc: Gary Hade <gary.hade@us.ibm.com>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Ingo Molnar <mingo@elte.hu>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      3d9befd2
    • A
      x86: acpi_pciprobe_dmi_table[] must be __devinitdata · 55b8d50c
      Adrian Bunk 提交于
      This patch fixes the following section mismatches with CONFIG_HOTPLUG=n:
      
      <--  snip  -->
      
      ...
      WARNING: vmlinux.o(.data+0x23640): Section mismatch: reference to .init.text.20:can_skip_ioresource_align (between 'acpi_pciprobe_dmi_table' and 'pcibios_irq_mask')
      WARNING: vmlinux.o(.data+0x2366c): Section mismatch: reference to .init.text.20:can_skip_ioresource_align (between 'acpi_pciprobe_dmi_table' and 'pcibios_irq_mask')
      WARNING: vmlinux.o(.data+0x23698): Section mismatch: reference to .init.text.20:can_skip_ioresource_align (between 'acpi_pciprobe_dmi_table' and 'pcibios_irq_mask')
      ...
      
      <--  snip  -->
      Signed-off-by: NAdrian Bunk <bunk@kernel.org>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      55b8d50c
  7. 20 10月, 2007 1 次提交
  8. 18 10月, 2007 1 次提交
  9. 13 10月, 2007 8 次提交
  10. 11 10月, 2007 2 次提交