1. 04 9月, 2015 2 次提交
  2. 03 9月, 2015 8 次提交
  3. 02 9月, 2015 2 次提交
  4. 01 9月, 2015 7 次提交
  5. 29 8月, 2015 8 次提交
  6. 28 8月, 2015 2 次提交
  7. 26 8月, 2015 6 次提交
  8. 25 8月, 2015 5 次提交
    • A
      perf tools: Update Intel PT documentation · 9d1bf02a
      Adrian Hunter 提交于
      Update Intel PT documentation to describe new features.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-26-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      9d1bf02a
    • A
      perf tools: Add Intel PT support for decoding TRACESTOP packets · 7eacca3e
      Adrian Hunter 提交于
      A TRACESTOP packet is produced when an Intel PT trace enters a defined
      region of the address space at which point the tracing stops.
      
      This patch just adds decoder support.
      
      Support for specifying TRACESTOP regions is left until later.
      
      For details refer to the June 2015 or later Intel 64 and IA-32
      Architectures SDM Chapter 36 Intel Processor Trace.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-25-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      7eacca3e
    • A
      perf tools: Add Intel PT support for using CYC packets · 0de802ab
      Adrian Hunter 提交于
      CYC packets are a new Intel PT feature.
      
      CYC packets provide even finer grain timestamp information than MTC and
      TSC packets.  A CYC packet contains the number of CPU cycles since the
      last CYC packet. Unlike MTC and TSC packets, CYC packets are only sent
      when another packet is also sent.
      
      Support for this feature is indicated by:
      
      /sys/bus/event_source/devices/intel_pt/caps/psb_cyc
      
      which contains "1" if the feature is supported and "0" otherwise.
      
      CYC packets can be requested using a PMU config term e.g. perf record -e
      intel_pt/cyc/u sleep 1
      
      The frequency of CYC packets can also be specified.  e.g. perf record -e
      intel_pt/cyc,cyc_thresh=2/u sleep 1
      
      CYC packets are not requested by default.
      
      Valid cyc_thresh values are given by:
      
      /sys/bus/event_source/devices/intel_pt/caps/cycle_thresholds
      
      which contains a hexadecimal value, the bits of which represent valid
      values e.g. bit 2 set means value 2 is valid.
      
      The value represents the minimum number of CPU cycles that must have
      passed before a CYC packet can be sent.  The number of CPU cycles is:
      
          2 ^ (value - 1)
      
      e.g. value 4 means 8 CPU cycles must pass before a CYC packet can be
      sent.  Note a CYC packet is still only sent when another packet is sent,
      not at, e.g. every 8 CPU cycles.
      
      If an invalid value is entered, the error message will give a list of
      valid values e.g.
      
          $ perf record -e intel_pt/cyc,cyc_thresh=15/u uname
          Invalid cyc_thresh for intel_pt. Valid values are: 0-12
      
      tools/perf/Documentation/intel-pt.txt is updated in a later patch as
      there are a number of new features being added.
      
      For more information refer to the June 2015 or later Intel 64 and IA-32
      Architectures SDM Chapter 36 Intel Processor Trace.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-24-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      0de802ab
    • A
      perf tools: Add Intel PT support for decoding CYC packets · cc336186
      Adrian Hunter 提交于
      CYC packets provide even finer grain timestamp information than MTC and
      TSC packets.  A CYC packet contains the number of CPU cycles since the
      last CYC packet.
      
      This patch just adds decoder support.  The CPU frequency can be related
      to TSC using the Maximum Non-Turbo Ratio in combination with the CBR
      (core-to-bus ratio) packet.  However more accuracy is achieved by simply
      interpolating the number of cycles between other timing packets like MTC
      or TSC.  This patch takes the latter approach.
      
      Support for a default value and validation of values is provided by a
      later patch. Also documentation is updated in a separate patch.
      
      For details refer to the June 2015 or later Intel 64 and IA-32
      Architectures SDM Chapter 36 Intel Processor Trace.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-23-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      cc336186
    • A
      perf tools: Add Intel PT support for using MTC packets · b45fc0bf
      Adrian Hunter 提交于
      MTC packets are a new Intel PT feature.
      
      MTC packets provide finer grain timestamp information than TSC packets.
      
      Support for this feature is indicated by:
      
        /sys/bus/event_source/devices/intel_pt/caps/mtc
      
      which contains "1" if the feature is supported and "0" otherwise.
      
      MTC packets can be requested using a PMU config term e.g. perf record -e
      intel_pt/mtc/u sleep 1
      
      The frequency of MTC packets can also be specified.  e.g. perf record -e
      intel_pt/mtc,mtc_period=2/u sleep 1
      
      The default value is 3 or the nearest lower value that is supported.  0
      is always supported.
      
      Valid values are given by:
      
      /sys/bus/event_source/devices/intel_pt/caps/mtc_periods
      
      which contains a hexadecimal value, the bits of which represent valid
      values e.g. bit 2 set means value 2 is valid.
      
      The value is converted to the MTC frequency as:
      
      	CTC-frequency / (2 ^ value)
      
      e.g. value 3 means one eighth of CTC-frequency
      
      Where CTC is the hardware crystal clock, the frequency of which can be
      related to TSC via values provided in cpuid leaf 0x15.
      
      If an invalid value is entered, the error message will give a list of
      valid values e.g.
      
      	$ perf record -e intel_pt/mtc_period=15/u uname
      	Invalid mtc_period for intel_pt. Valid values are: 0,3,6,9
      
      tools/perf/Documentation/intel-pt.txt is updated in a later patch as
      there are a number of new features being added.
      
      For more information refer to the June 2015 or later Intel 64 and IA-32
      Architectures SDM Chapter 36 Intel Processor Trace.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-22-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      b45fc0bf