1. 05 5月, 2010 5 次提交
    • E
      x86, acpi/irq: Handle isa irqs that are not identity mapped to gsi's. · 988856ee
      Eric W. Biederman 提交于
      ACPI irq source overrides are allowed for the 16 isa irqs and are
      allowed to map any gsi to any isa irq.  A few motherboards have been
      seen to take advantage of this and put the isa irqs on the 2nd or
      3rd ioapic.  This causes some problems, most notably the fact
      that we can not use any gsi < 16.
      
      To correct this move the gsis that are not isa irqs and have
      a gsi number < 16 into the linux irq space just past gsi_end.
      This is what the es7000 platform is doing today.  Moving only the
      low 16 gsis above the rest of the gsi's only penalizes weird
      platforms, leaving sane acpi implementations with a 1-1 mapping
      of gsis and irqs.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      LKML-Reference: <1269936436-7039-14-git-send-email-ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      988856ee
    • E
      x86, ioapic: Simplify probe_nr_irqs_gsi. · 4afc51a8
      Eric W. Biederman 提交于
      Use the global gsi_end value now that all ioapics have
      valid gsi numbers instead of a combination of acpi_probe_gsi
      and walking all of the ioapics and couting their number of
      entries by hand if acpi_probe_gsi gave us an answer we did
      not like.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      LKML-Reference: <1269936436-7039-13-git-send-email-ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      4afc51a8
    • E
      x86, acpi/irq: Generalize mp_config_acpi_legacy_irqs · 0fd52670
      Eric W. Biederman 提交于
      Remove the assumption that there is not an override for isa irq 0.
      Instead lookup the gsi and from that lookup the ioapic and pin of each
      isa irq indivdually.
      
      In general this should not have any behavioural affect but in
      perverse cases this gets all of the details correct, instead of
      doing something weird.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      LKML-Reference: <1269936436-7039-5-git-send-email-ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      0fd52670
    • E
      x86, acpi/irq: Fix acpi_sci_ioapic_setup so it has both bus_irq and gsi · 9d2062b8
      Eric W. Biederman 提交于
      Currently acpi_sci_ioapic_setup calls mp_override_legacy_irq with
      bus_irq == gsi, which is wrong if we are comming from an override
      Instead pass the bus_irq into acpi_sci_ioapic_setup.
      
      This fix was inspired by a similar fix from:
      Yinghai Lu <yinghai@kernel.org>
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      LKML-Reference: <1269936436-7039-4-git-send-email-ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      9d2062b8
    • E
      x86, acpi/irq: Introduce apci_isa_irq_to_gsi · 2c2df841
      Eric W. Biederman 提交于
      There are a number of cases where the current code makes the assumption
      that isa irqs identity map to the first 16 acpi global system intereupts.
      In most instances that assumption is correct as that is the required
      behaviour in dual i8259 mode and the default behavior in ioapic mode.
      
      However there are some systems out there that take advantage of acpis
      interrupt remapping  for the isa irqs to have a completely different
      mapping of isa_irq to gsi.
      
      Introduce acpi_isa_irq_to_gsi to perform this mapping explicitly in the
      code that needs it.  Initially this will be just the current assumed
      identity mapping to ensure it's introduction does not cause regressions.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      LKML-Reference: <1269936436-7039-1-git-send-email-ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      2c2df841
  2. 30 3月, 2010 1 次提交
    • T
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking... · 5a0e3ad6
      Tejun Heo 提交于
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
      
      percpu.h is included by sched.h and module.h and thus ends up being
      included when building most .c files.  percpu.h includes slab.h which
      in turn includes gfp.h making everything defined by the two files
      universally available and complicating inclusion dependencies.
      
      percpu.h -> slab.h dependency is about to be removed.  Prepare for
      this change by updating users of gfp and slab facilities include those
      headers directly instead of assuming availability.  As this conversion
      needs to touch large number of source files, the following script is
      used as the basis of conversion.
      
        http://userweb.kernel.org/~tj/misc/slabh-sweep.py
      
      The script does the followings.
      
      * Scan files for gfp and slab usages and update includes such that
        only the necessary includes are there.  ie. if only gfp is used,
        gfp.h, if slab is used, slab.h.
      
      * When the script inserts a new include, it looks at the include
        blocks and try to put the new include such that its order conforms
        to its surrounding.  It's put in the include block which contains
        core kernel includes, in the same order that the rest are ordered -
        alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
        doesn't seem to be any matching order.
      
      * If the script can't find a place to put a new include (mostly
        because the file doesn't have fitting include block), it prints out
        an error message indicating which .h file needs to be added to the
        file.
      
      The conversion was done in the following steps.
      
      1. The initial automatic conversion of all .c files updated slightly
         over 4000 files, deleting around 700 includes and adding ~480 gfp.h
         and ~3000 slab.h inclusions.  The script emitted errors for ~400
         files.
      
      2. Each error was manually checked.  Some didn't need the inclusion,
         some needed manual addition while adding it to implementation .h or
         embedding .c file was more appropriate for others.  This step added
         inclusions to around 150 files.
      
      3. The script was run again and the output was compared to the edits
         from #2 to make sure no file was left behind.
      
      4. Several build tests were done and a couple of problems were fixed.
         e.g. lib/decompress_*.c used malloc/free() wrappers around slab
         APIs requiring slab.h to be added manually.
      
      5. The script was run on all .h files but without automatically
         editing them as sprinkling gfp.h and slab.h inclusions around .h
         files could easily lead to inclusion dependency hell.  Most gfp.h
         inclusion directives were ignored as stuff from gfp.h was usually
         wildly available and often used in preprocessor macros.  Each
         slab.h inclusion directive was examined and added manually as
         necessary.
      
      6. percpu.h was updated not to include slab.h.
      
      7. Build test were done on the following configurations and failures
         were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
         distributed build env didn't work with gcov compiles) and a few
         more options had to be turned off depending on archs to make things
         build (like ipr on powerpc/64 which failed due to missing writeq).
      
         * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
         * powerpc and powerpc64 SMP allmodconfig
         * sparc and sparc64 SMP allmodconfig
         * ia64 SMP allmodconfig
         * s390 SMP allmodconfig
         * alpha SMP allmodconfig
         * um on x86_64 SMP allmodconfig
      
      8. percpu.h modifications were reverted so that it could be applied as
         a separate patch and serve as bisection point.
      
      Given the fact that I had only a couple of failures from tests on step
      6, I'm fairly confident about the coverage of this conversion patch.
      If there is a breakage, it's likely to be something in one of the arch
      headers which should be easily discoverable easily on most builds of
      the specific arch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
      5a0e3ad6
  3. 15 3月, 2010 3 次提交
  4. 20 2月, 2010 1 次提交
    • T
      x86: Move pci init function to x86_init · b72d0db9
      Thomas Gleixner 提交于
      The PCI initialization in pci_subsys_init() is a mess. pci_numaq_init,
      pci_acpi_init, pci_visws_init and pci_legacy_init are called and each
      implementation checks and eventually modifies the global variable
      pcibios_scanned.
      
      x86_init functions allow us to do this more elegant. The pci.init
      function pointer is preset to pci_legacy_init. numaq, acpi and visws
      can modify the pointer in their early setup functions. The functions
      return 0 when they did the full initialization including bus scan. A
      non zero return value indicates that pci_legacy_init needs to be
      called either because the selected function failed or wants the
      generic bus scan in pci_legacy_init to happen (e.g. visws).
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      LKML-Reference: <43F901BD926A4E43B106BF17856F07559FB80CFE@orsmsx508.amr.corp.intel.com>
      Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NJacob Pan <jacob.jun.pan@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      b72d0db9
  5. 16 2月, 2010 1 次提交
  6. 11 2月, 2010 2 次提交
  7. 10 2月, 2010 1 次提交
    • S
      x86, apic: Don't use logical-flat mode when CPU hotplug may exceed 8 CPUs · 681ee44d
      Suresh Siddha 提交于
      We need to fall back from logical-flat APIC mode to physical-flat mode
      when we have more than 8 CPUs.  However, in the presence of CPU
      hotplug(with bios listing not enabled but possible cpus as disabled cpus in
      MADT), we have to consider the number of possible CPUs rather than
      the number of current CPUs; otherwise we may cross the 8-CPU boundary
      when CPUs are added later.
      
      32bit apic code can use more cleanups (like the removal of vendor checks in
      32bit default_setup_apic_routing()) and more unifications with 64bit code.
      Yinghai has some patches in works already. This patch addresses the boot issue
      that is reported in the virtualization guest context.
      
      [ hpa: incorporated function annotation feedback from Yinghai Lu ]
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      LKML-Reference: <1265767304.2833.19.camel@sbs-t61.sc.intel.com>
      Acked-by: NShaohui Zheng <shaohui.zheng@intel.com>
      Reviewed-by: NYinghai Lu <yinghai@kernel.org>
      Cc: <stable@kernel.org>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      681ee44d
  8. 07 1月, 2010 1 次提交
  9. 04 12月, 2009 1 次提交
  10. 29 8月, 2009 1 次提交
    • F
      ACPI, x86: expose some IO-APIC routines when CONFIG_ACPI=n · 2a4ab640
      Feng Tang 提交于
      Some IO-APIC routines are ACPI specific now, but need to
      be exposed when CONFIG_ACPI=n for the benefit of SFI.
      
      Remove #ifdef ACPI around these routines:
      
      io_apic_get_unique_id(int ioapic, int apic_id);
      io_apic_get_version(int ioapic);
      io_apic_get_redir_entries(int ioapic);
      
      Move these routines from ACPI-specific boot.c to io_apic.c:
      
      uniq_ioapic_id(u8 id)
      mp_find_ioapic()
      mp_find_ioapic_pin()
      mp_register_ioapic()
      
      Also, since uniq_ioapic_id() is now no longer static,
      re-name it to io_apic_unique_id() for consistency
      with the other public io_apic routines.
      
      For simplicity, do not #ifdef the resulting code ACPI || SFI,
      thought that could be done in the future if it is important
      to optimize the !ACPI !SFI IO-APIC x86 kernel for size.
      Signed-off-by: NFeng Tang <feng.tang@intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Cc: x86@kernel.org
      2a4ab640
  11. 28 8月, 2009 1 次提交
  12. 15 7月, 2009 1 次提交
  13. 13 6月, 2009 3 次提交
  14. 02 6月, 2009 1 次提交
    • N
      x86: Print real IOAPIC version for x86-64 · 58f892e0
      Naga Chumbalkar 提交于
      Fix the fact that the IOAPIC version number in the x86_64 code path always
      gets assigned to 0, instead of the correct value.
      
      Before the patch: (from "dmesg" output):
      
       ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
       IOAPIC[0]: apic_id 8, version 0, address 0xfec00000, GSI 0-23     <---
      
       After the patch:
       ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
       IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23    <---
      
      History:
      
      io_apic_get_version() was compiled out of the x86_64 code path in the commit
      f2c2cca3:
      
      Author: Andi Kleen <ak@suse.de>
      Date:   Tue Sep 26 10:52:37 2006 +0200
      
          [PATCH] Remove APIC version/cpu capability mpparse checking/printing
      
          ACPI went to great trouble to get the APIC version and CPU capabilities
          of different CPUs before passing them to the mpparser. But all
          that data was used was to print it out.  Actually it even faked some data
          based on the boot cpu, not on the actual CPU being booted.
      
          Remove all this code because it's not needed.
      
          Cc: len.brown@intel.com
      
      At the time, the IOAPIC version number was deliberately not printed
      in the x86_64 code path. However, after the x86 and x86_64 files were
      merged, the net result is that the IOAPIC version is printed incorrectly
      in the x86_64 code path.
      
      The patch below provides a fix. I have tested it with acpi, and with
      acpi=off, and did not see any problems.
      Signed-off-by: NNaga Chumbalkar <nagananda.chumbalkar@hp.com>
      Acked-by: NYinghai Lu <yhlu.kernel@gmail.com>
      LKML-Reference: <20090416014230.4885.94926.sendpatchset@localhost.localdomain>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      *************************
      58f892e0
  15. 18 5月, 2009 2 次提交
    • Y
      x86, irq: don't call mp_config_acpi_gsi() if update_mptable is not enabled · f1bdb523
      Yinghai Lu 提交于
      Len expressed concern that the update_mptable feature has
      side-effects on the ACPI code.
      
      Make it sure explicitly that the code only ever gets called if
      the (default disabled) update_mptable boot quirk option is
      disabled.
      
      [ Impact: isolate the update_mptable feature from ACPI code more ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A0DC832.5090200@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f1bdb523
    • Y
      x86, apic: introduce io_apic_irq_attr · e5198075
      Yinghai Lu 提交于
      according to Ingo, io_apic irq-setup related functions have too many
      parameters with a repetitive signature.
      
      So reduce related funcs to get less params by passing a pointer
      to a newly defined io_apic_irq_attr structure.
      
      v2: io_apic_irq ==> irq_attr
          triggering ==> trigger
      
      v3: add set_io_apic_irq_attr
      
      [ Impact: cleanup ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A08ACD3.2070401@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e5198075
  16. 11 5月, 2009 3 次提交
    • Y
      x86/acpi: move pin_programmed bit map to io_apic.c · bdfe8ac1
      Yinghai Lu 提交于
      Prepare to call setup_io_apic_routing() in pcibios_irq_enable()
      also remove not needed member apic_id.
      
      [ Impact: clean up, prepare for future change ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C3DD.3050104@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      bdfe8ac1
    • Y
      x86/acpi: call mp_config_acpi_gsi() in mp_register_gsi() · a31f8205
      Yinghai Lu 提交于
      The patch to call mp_config_acpi_gsi() from the ACPI IRQ registration
      code never got mainline because there were open discussions about it.
      
      This call is needed to properly update the kernel's copy of the mptable,
      when the update_mptable boot parameter is needed.
      
      Now that the dust has settled with the APIC unification, and since there
      were no objections when the patch was re-submitted, try this again.
      
      [ Impact: fix the update_mptable boot parameter ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C387.7090103@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a31f8205
    • Y
      x86/acpi: remove irq-compression trick on 32-bit · b9e0353f
      Yinghai Lu 提交于
      We already have a per cpu vector on 32-bit via recent changes, and
      don't need this trick any more (which trick obfuscates the real GSI
      mappings and which only triggers on larger systems to begin with):
      
      On 3 ioapic system (24 per ioapic) before patch I got:
      
      ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71
      IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 64 Mode:1 Active:1)
      pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 64
      ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67
      IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 65 Mode:1 Active:1)
      pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66
      IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1)
      pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65
      IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 67 Mode:1 Active:1)
      pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64
      IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 68 Mode:1 Active:1)
      pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 67
      pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 68
      pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 65
      
      after the patch we get:
      
      ACPI: PCI Interrupt Link [ILSB] enabled at IRQ 71
      IOAPIC[2]: Set routing entry (10-23 -> 0xa9 -> IRQ 71 Mode:1 Active:1)
      pci 0000:80:01.1: PCI INT A -> Link[ILSB] -> GSI 71 (level, low) -> IRQ 71
      ACPI: PCI Interrupt Link [LE5B] enabled at IRQ 67
      IOAPIC[2]: Set routing entry (10-19 -> 0xb1 -> IRQ 67 Mode:1 Active:1)
      pci 0000:83:00.0: PCI INT B -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      ACPI: PCI Interrupt Link [LE5A] enabled at IRQ 66
      IOAPIC[2]: Set routing entry (10-18 -> 0xb9 -> IRQ 66 Mode:1 Active:1)
      pci 0000:83:00.1: PCI INT A -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      ACPI: PCI Interrupt Link [LE5D] enabled at IRQ 65
      IOAPIC[2]: Set routing entry (10-17 -> 0xc1 -> IRQ 65 Mode:1 Active:1)
      pci 0000:84:00.0: PCI INT B -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      ACPI: PCI Interrupt Link [LE5C] enabled at IRQ 64
      IOAPIC[2]: Set routing entry (10-16 -> 0xc9 -> IRQ 64 Mode:1 Active:1)
      pci 0000:84:00.1: PCI INT A -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:87:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:87:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      pci 0000:88:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:88:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      pci 0000:8b:00.0: PCI INT B -> Link[LE5A] -> GSI 66 (level, low) -> IRQ 66
      pci 0000:8b:00.1: PCI INT A -> Link[LE5D] -> GSI 65 (level, low) -> IRQ 65
      pci 0000:8c:00.0: PCI INT B -> Link[LE5C] -> GSI 64 (level, low) -> IRQ 64
      pci 0000:8c:00.1: PCI INT A -> Link[LE5B] -> GSI 67 (level, low) -> IRQ 67
      
      As it can be seen that GSIs now get mapped lineary.
      
      [ Impact: simplify irq number mapping on bigger 32-bit systems ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Len Brown <lenb@kernel.org>
      LKML-Reference: <4A01C35C.7060207@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      b9e0353f
  17. 28 4月, 2009 1 次提交
    • Y
      irq: change ACPI GSI APIs to also take a device argument · a2f809b0
      Yinghai Lu 提交于
      We want to use dev_to_node() later on, to be aware of the 'home node'
      of the GSI in question.
      
      [ Impact: cleanup, prepare the IRQ code to be more NUMA aware ]
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Acked-by: NLen Brown <lenb@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: linux-acpi@vger.kernel.org
      Cc: linux-ia64@vger.kernel.org
      LKML-Reference: <49F65560.20904@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a2f809b0
  18. 04 4月, 2009 2 次提交
  19. 18 2月, 2009 2 次提交
  20. 10 2月, 2009 2 次提交
  21. 09 2月, 2009 5 次提交