Signed-off-by: NJeff McGee <jeff.mcgee@intel.com>
Reviewed-by: NImre Deak <imre.deak@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

For BXT, DDI buf idle timeout delay needs to be increased to 16us.

Since this is a timeout value and we return as soon as the condition is
realized, no penalty incurred for other platforms.

v2:
- remove TIMEOUT macro used only at a single place (Daniel)
Suggested-by: NSatheeshakrishna M <satheeshakrishna.m@intel.com>
Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: NVandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Reviewed-by: NJani Nikula <jani.nikula@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: NNick Hoath <nicholas.hoath@intel.com>
Reviewed-by: NImre Deak <imre.deak@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Adds framework for Broxton HW WAs
Signed-off-by: NNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.

v2:
- add comment explaining how the problem with WC mapping manifests
  (Daniel)
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Pipe A and b have 4 planes.
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
    argument.
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

The caching options for page table entries have remained the same as
Cherryview. This patch fixes it so the right code path is taken on BXT.

v2: Fix up commit message (Mike)
Signed-off-by: NSumit Singh <sumit.k.singh@intel.com>
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Adding IS_BROXTON macro for broxton specific implementation.
Signed-off-by: NSatheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.

Motivated by Rodrigo's request to check FBC support on BXT.
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Enable FBC feature on Broxton

Issue: VIZ-3784
Signed-off-by: NDaisy Sun <daisy.sun@intel.com>
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

v2: Switch to info->ring_mask and add VEBOX support.
v3: Fold in update from Damien.
v4: Add GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS
v5: set no-LLC (imre)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1,v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v4)
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Reference the power domain incase vop power down when
in use.
Signed-off-by: NMark Yao <yzq@rock-chips.com>

drm/rockchip already has support for disabling all displays on suspend
and enabling them on resume.

Disable automatic VT switching on suspend by the pm console tracking
layer.

Tested on veyron, used `echo mem > sys/power/state`
  => verified no VT switch
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>

Register connectors with userspace after all components are bound.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Reviewed-by: NDominik Behr <dbehr@chromium.org>

drm_connector_get_name -> connector->name
This patch is necessary to make X11 see screens it seems.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The function disables the dclk at the beginning, so don't simply return
when an error happens, but instead enable the clock again, so that
enable and disable calls are balanced.

ret_clk is introduced to hold the clk_enable result and not mangle the
original error code.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges
additionally to the typical values for pixel clock rate (64.3-82 MHz)
and blanking intervals (54-681 clock cycles horizontally, 3-23 lines
vertically).

This patch replaces this panel's display mode with the display timing
information to describe acceptable timings. Since the HSYNC and VSYNC
are unused, the distribution between front porches, back porches, and
sync pulse lengths was chosen at will.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The simple panel driver's ->get_modes() implementation calculates the
display mode list from the typical timings and the ->get_timings()
implementation returns the timings to the connected encoder for mode
validation and fixup.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
[treding@nvidia.com: select VIDEOMODE_HELPERS]
Signed-off-by: NThierry Reding <treding@nvidia.com>

This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch adds the bus_format field to the GPG482739QS5 panel structure.
Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The AUO b101ean01 panel is a 10.1" 1280x800 panel which can be supported
by the simple panel driver.
Signed-off-by: NHuang Lin <hl@rock-chips.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Innolux ZJ070NA-01P is a 7.0" TFT LCD panel with an integrated LED
backlight unit.

This panel is used on the Technexion Toucan.
Signed-off-by: NMichael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Innolux AT043TN24 4.3" WQVGA TFT LCD panel.
This panel with backlight is found in PDA 4.3" LCD screen (TM43xx series for
instance).
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Shelly SCA07010-BFN-LNN is a 7.0" WVGA TFT LCD panel.
This panel with backlight is found in PDA 7" LCD screen (TM70xx series for
instance).
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This panel is used by the Nyan Blaze board and can be supported by the
simple-panel driver.
Signed-off-by: NStéphane Marchesin <marcheu@chromium.org>
[tomeu.vizoso@collabora.com: add device tree binding document]
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

As there isn't a way for the firmware on the Nyan Chromebooks to hand
over the display to the kernel, and the kernel isn't redoing the whole
configuration at present.

With this patch, the SOR is brought to a known state and we get correct
display on every boot.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Name the fields of the SOR_SEQ_CTL register consistently.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Resets on Tegra are synchronous, so keep the clock enabled while
asserting the reset.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This function is called by output drivers so should be documented. While
at it, move it to a more appropriate location.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The ->mode_set() and ->mode_set_base() callbacks are no longer used with
full atomic mode-setting drivers, so remove them.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The tegra_dc_setup_clock() function is unused after the conversion to
atomic mode-setting, so remove it.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Instead of duplicating the code, make use of the newly introduced atomic
state duplicate and destroy helpers. This allows changes to the base
atomic state handling to automatically propagate to the Tegra driver and
thereby prevent breakage resulting from both copies going out of sync.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Drivers that subclass CRTC, plane or connector state need to carefully
duplicate the code that the atomic helpers have. This is bound to cause
breakage eventually because it requires auditing all drivers and update
them when code is added to the helpers.

In order to avoid that, implement new helpers that perform the required
steps when copying and destroying state. These new helpers are exported
so that state-subclassing drivers can use them. The default helpers are
implemented using them as well, providing a single location that needs
to be changed when adding to base atomic states.
Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The display controller on Tegra can use syncpoints to count VBLANK
events. syncpoints are 32-bit unsigned integers, so well suited as
VBLANK counters.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This function is used to read the current value of the syncpt and is
useful in situations where drivers don't schedule work and wait for the
syncpoint to increment. One particular use-case is using the syncpoint
as a VBLANK counter.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Signed-off-by: NThierry Reding <treding@nvidia.com>

Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.
Signed-off-by: NThierry Reding <treding@nvidia.com>