1. 23 10月, 2012 1 次提交
  2. 21 9月, 2012 1 次提交
  3. 20 7月, 2012 1 次提交
  4. 02 6月, 2012 1 次提交
  5. 21 3月, 2012 1 次提交
  6. 23 1月, 2012 1 次提交
  7. 06 1月, 2012 1 次提交
    • J
      drm/radeon: GPU virtual memory support v22 · 721604a1
      Jerome Glisse 提交于
      Virtual address space are per drm client (opener of /dev/drm).
      Client are in charge of virtual address space, they need to
      map bo into it by calling DRM_RADEON_GEM_VA ioctl.
      
      First 16M of virtual address space is reserved by the kernel.
      
      Once using 2 level page table we should be able to have a small
      vram memory footprint for each pt (there would be one pt for all
      gart, one for all vram and then one first level for each virtual
      address space).
      
      Plan include using the sub allocator for a common vm page table
      area and using memcpy to copy vm page table in & out. Or use
      a gart object and copy things in & out using dma.
      
      v2: agd5f fixes:
      - Add vram base offset for vram pages.  The GPU physical address of a
      vram page is FB_OFFSET + page offset.  FB_OFFSET is 0 on discrete
      cards and the physical bus address of the stolen memory on
      integrated chips.
      - VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
      
      v3: agd5f:
      - integrate with the semaphore/multi-ring stuff
      
      v4:
      - rebase on top ttm dma & multi-ring stuff
      - userspace is now in charge of the address space
      - no more specific cs vm ioctl, instead cs ioctl has a new
        chunk
      
      v5:
      - properly handle mem == NULL case from move_notify callback
      - fix the vm cleanup path
      
      v6:
      - fix update of page table to only happen on valid mem placement
      
      v7:
      - add tlb flush for each vm context
      - add flags to define mapping property (readable, writeable, snooped)
      - make ring id implicit from ib->fence->ring, up to each asic callback
        to then do ring specific scheduling if vm ib scheduling function
      
      v8:
      - add query for ib limit and kernel reserved virtual space
      - rename vm->size to max_pfn (maximum number of page)
      - update gem_va ioctl to also allow unmap operation
      - bump kernel version to allow userspace to query for vm support
      
      v9:
      - rebuild page table only when bind and incrementaly depending
        on bo referenced by cs and that have been moved
      - allow virtual address space to grow
      - use sa allocator for vram page table
      - return invalid when querying vm limit on non cayman GPU
      - dump vm fault register on lockup
      
      v10: agd5f:
      - Move the vm schedule_ib callback to a standalone function, remove
        the callback and use the existing ib_execute callback for VM IBs.
      
      v11:
      - rebase on top of lastest Linus
      
      v12: agd5f:
      - remove spurious backslash
      - set IB vm_id to 0 in radeon_ib_get()
      
      v13: agd5f:
      - fix handling of RADEON_CHUNK_ID_FLAGS
      
      v14:
      - fix va destruction
      - fix suspend resume
      - forbid bo to have several different va in same vm
      
      v15:
      - rebase
      
      v16:
      - cleanup left over of vm init/fini
      
      v17: agd5f:
      - cs checker
      
      v18: agd5f:
      - reworks the CS ioctl to better support multiple rings and
      VM.  Rather than adding a new chunk id for VM, just re-use the
      IB chunk id and add a new flags for VM mode.  Also define additional
      dwords for the flags chunk id to define the what ring we want to use
      (gfx, compute, uvd, etc.) and the priority.
      
      v19:
      - fix cs fini in weird case of no ib
      - semi working flush fix for ni
      - rebase on top of sa allocator changes
      
      v20: agd5f:
      - further CS ioctl cleanups from Christian's comments
      
      v21: agd5f:
      - integrate CS checker improvements
      
      v22: agd5f:
      - final cleanups for release, only allow VM CS on cayman
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      721604a1
  8. 21 12月, 2011 2 次提交
  9. 02 7月, 2011 1 次提交
  10. 24 5月, 2011 1 次提交
  11. 22 5月, 2011 1 次提交
  12. 03 3月, 2011 4 次提交
  13. 07 1月, 2011 1 次提交
  14. 15 6月, 2009 1 次提交
    • J
      drm/radeon: introduce kernel modesetting for radeon hardware · 771fe6b9
      Jerome Glisse 提交于
      Add kernel modesetting support to radeon driver, use the ttm memory
      manager to manage memory and DRM/GEM to provide userspace API.
      In order to avoid backward compatibility issue and to allow clean
      design and code the radeon kernel modesetting use different code path
      than old radeon/drm driver.
      
      When kernel modesetting is enabled the IOCTL of radeon/drm
      driver are considered as invalid and an error message is printed
      in the log and they return failure.
      
      KMS enabled userspace will use new API to talk with the radeon/drm
      driver. The new API provide functions to create/destroy/share/mmap
      buffer object which are then managed by the kernel memory manager
      (here TTM). In order to submit command to the GPU the userspace
      provide a buffer holding the command stream, along this buffer
      userspace have to provide a list of buffer object used by the
      command stream. The kernel radeon driver will then place buffer
      in GPU accessible memory and will update command stream to reflect
      the position of the different buffers.
      
      The kernel will also perform security check on command stream
      provided by the user, we want to catch and forbid any illegal use
      of the GPU such as DMA into random system memory or into memory
      not owned by the process supplying the command stream. This part
      of the code is still incomplete and this why we propose that patch
      as a staging driver addition, future security might forbid current
      experimental userspace to run.
      
      This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX
      (radeon up to X1950). Works is underway to provide support for R6XX,
      R7XX and newer hardware (radeon from HD2XXX to HD4XXX).
      
      Authors:
          Jerome Glisse <jglisse@redhat.com>
          Dave Airlie <airlied@redhat.com>
          Alex Deucher <alexdeucher@gmail.com>
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      771fe6b9
  15. 14 7月, 2008 1 次提交
    • D
      drm: reorganise drm tree to be more future proof. · c0e09200
      Dave Airlie 提交于
      With the coming of kernel based modesetting and the memory manager stuff,
      the everything in one directory approach was getting very ugly and
      starting to be unmanageable.
      
      This restructures the drm along the lines of other kernel components.
      
      It creates a drivers/gpu/drm directory and moves the hw drivers into
      subdirectores. It moves the includes into an include/drm, and
      sets up the unifdef for the userspace headers we should be exporting.
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      c0e09200
  16. 02 1月, 2006 1 次提交
  17. 11 11月, 2005 1 次提交
  18. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4