1. 18 4月, 2008 1 次提交
  2. 17 4月, 2008 1 次提交
  3. 14 2月, 2008 1 次提交
  4. 08 11月, 2007 1 次提交
    • B
      [POWERPC] Fix cache line vs. block size confusion · 20474abd
      Benjamin Herrenschmidt 提交于
      We had an historical confusion in the kernel between cache line
      and cache block size. The former is an implementation detail of
      the L1 cache which can be useful for performance optimisations,
      the later is the actual size on which the cache control
      instructions operate, which can be different.
      
      For some reason, we had a weird hack reading the right property
      on powermac and the wrong one on any other 64 bits (32 bits is
      unaffected as it only uses the cputable for cache block size
      infos at this stage).
      
      This fixes the booting-without-of.txt documentation to mention
      the right properties, and fixes the 64 bits initialization code
      to look for the block size first, with a fallback to the line
      size if the property is missing.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      20474abd
  5. 17 10月, 2007 2 次提交
    • A
      [POWERPC] Quieten cache information at boot · 9697add0
      Anton Blanchard 提交于
      After 6 years the ppc64 kernel still thinks its important to tell me my
      cache line size is 0x80 bytes. I think most people who care know that by
      now. The rest probably cant even understand the hex output.
      
      Since we might have misconfigured firmware or cpus that have a linesize
      that isnt 128 bytes, I still print it out for those cases. If people
      would prefer to remove it completely, lets do it.
      
      Also for lpar remove the htab_address printout since its not used.
      
      Anton
      ppc64 boot log usability expert
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      9697add0
    • M
      Convert cpu_sibling_map to be a per cpu variable · d5a7430d
      Mike Travis 提交于
      Convert cpu_sibling_map from a static array sized by NR_CPUS to a per_cpu
      variable.  This saves sizeof(cpumask_t) * NR unused cpus.  Access is mostly
      from startup and CPU HOTPLUG functions.
      Signed-off-by: NMike Travis <travis@sgi.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Christoph Lameter <clameter@sgi.com>
      Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      d5a7430d
  6. 11 10月, 2007 1 次提交
  7. 13 9月, 2007 1 次提交
  8. 19 7月, 2007 1 次提交
  9. 25 6月, 2007 1 次提交
  10. 03 5月, 2007 1 次提交
  11. 13 4月, 2007 2 次提交
  12. 04 12月, 2006 3 次提交
    • P
      [POWERPC] Distinguish POWER6 partition modes and tell userspace · 974a76f5
      Paul Mackerras 提交于
      This adds code to look at the properties firmware puts in the device
      tree to determine what compatibility mode the partition is in on
      POWER6 machines, and set the ELF aux vector AT_HWCAP and AT_PLATFORM
      entries appropriately.
      
      Specifically, we look at the cpu-version property in the cpu node(s).
      If that contains a "logical" PVR value (of the form 0x0f00000x), we
      call identify_cpu again with this PVR value.  A value of 0x0f000001
      indicates the partition is in POWER5+ compatibility mode, and a value
      of 0x0f000002 indicates "POWER6 architected" mode, with various
      extensions disabled.  We also look for various other properties:
      ibm,dfp, ibm,purr and ibm,spurr.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      974a76f5
    • B
      [POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits · 4cb3cee0
      Benjamin Herrenschmidt 提交于
      This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
      and PIO) and provides a generic way for other platforms to do so (we
      have need to do that for various other platforms).
      
      While reworking the IO ops, I ended up doing some spring cleaning in
      io.h and eeh.h which I might want to split into 2 or 3 patches (among
      others, eeh.h had a lot of useless stuff in it).
      
      A side effect is that EEH for PIO should work now (it used to pass IO
      ports down to the eeh address check functions which is bogus).
      
      Also, new are MMIO "repeat" ops, which other archs like ARM already had,
      and that we have too now: readsb, readsw, readsl, writesb, writesw,
      writesl.
      
      In the long run, I might also make EEH use the hooks instead
      of wrapping at the toplevel, which would make things even cleaner and
      relegate EEH completely in platforms/iseries, but we have to measure the
      performance impact there (though it's really only on MMIO reads)
      
      Since I also need to hook on ioremap, I shuffled the functions a bit
      there. I introduced ioremap_flags() to use by drivers who want to pass
      explicit flags to ioremap (and it can be hooked). The old __ioremap() is
      still there as a low level and cannot be hooked, thus drivers who use it
      should migrate unless they know they want the low level version.
      
      The patch "arch provides generic iomap missing accessors" (should be
      number 4 in this series) is a pre-requisite to provide full iomap
      API support with this patch.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      4cb3cee0
    • B
      [POWERPC] Refactor 64 bits DMA operations · 12d04eef
      Benjamin Herrenschmidt 提交于
      This patch completely refactors DMA operations for 64 bits powerpc. 32 bits
      is untouched for now.
      
      We use the new dev_archdata structure to add the dma operations pointer
      and associated data to struct device. While at it, we also add the OF node
      pointer and numa node. In the future, we might want to look into merging
      that with pci_dn as well.
      
      The old vio, pci-iommu and pci-direct DMA ops are gone. They are now replaced
      by a set of generic iommu and direct DMA ops (non PCI specific) that can be
      used by bus types. The toplevel implementation is now inline.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      12d04eef
  13. 13 11月, 2006 2 次提交
  14. 25 10月, 2006 2 次提交
    • B
      [POWERPC] Support feature fixups in vdso's · 0909c8c2
      Benjamin Herrenschmidt 提交于
      This patch reworks the feature fixup mecanism so vdso's can be fixed up.
      The main issue was that the construct:
      
              .long   label  (or .llong on 64 bits)
      
      will not work in the case of a shared library like the vdso. It will
      generate an empty placeholder in the fixup table along with a reloc,
      which is not something we can deal with in the vdso.
      
      The idea here (thanks Alan Modra !) is to instead use something like:
      
      1:
              .long   label - 1b
      
      That is, the feature fixup tables no longer contain addresses of bits of
      code to patch, but offsets of such code from the fixup table entry
      itself. That is properly resolved by ld when building the .so's. I've
      modified the fixup mecanism generically to use that method for the rest
      of the kernel as well.
      
      Another trick is that the 32 bits vDSO included in the 64 bits kernel
      need to have a table in the 64 bits format. However, gas does not
      support 32 bits code with a statement of the form:
      
              .llong  label - 1b  (Or even just .llong label)
      
      That is, it cannot emit the right fixup/relocation for the linker to use
      to assign a 32 bits address to an .llong field. Thus, in the specific
      case of the 32 bits vdso built as part of the 64 bits kernel, we are
      using a modified macro that generates:
      
              .long   0xffffffff
              .llong  label - 1b
      
      Note that is assumes that the value is negative which is enforced by
      the .lds (those offsets are always negative as the .text is always
      before the fixup table and gas doesn't support emiting the reloc the
      other way around).
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      0909c8c2
    • B
      [POWERPC] Consolidate feature fixup code · 42c4aaad
      Benjamin Herrenschmidt 提交于
      There are currently two versions of the functions for applying the
      feature fixups, one for CPU features and one for firmware features. In
      addition, they are both in assembly and with separate implementations
      for 32 and 64 bits. identify_cpu() is also implemented in assembly and
      separately for 32 and 64 bits.
      
      This patch replaces them with a pair of C functions. The call sites are
      slightly moved on ppc64 as well to be called from C instead of from
      assembly, though it's a very small change, and thus shouldn't cause any
      problem.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: NOlof Johansson <olof@lixom.net>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      42c4aaad
  15. 16 10月, 2006 1 次提交
    • P
      [POWERPC] Lazy interrupt disabling for 64-bit machines · d04c56f7
      Paul Mackerras 提交于
      This implements a lazy strategy for disabling interrupts.  This means
      that local_irq_disable() et al. just clear the 'interrupts are
      enabled' flag in the paca.  If an interrupt comes along, the interrupt
      entry code notices that interrupts are supposed to be disabled, and
      clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
      flag in the paca, and returns.  This means that interrupts only
      actually get disabled in the processor when an interrupt comes along.
      
      When interrupts are enabled by local_irq_enable() et al., the code
      sets the interrupts-enabled flag in the paca, and then checks whether
      interrupts got hard-disabled.  If so, it also sets the EE bit in the
      MSR to hard-enable the interrupts.
      
      This has the potential to improve performance, and also makes it
      easier to make a kernel that can boot on iSeries and on other 64-bit
      machines, since this lazy-disable strategy is very similar to the
      soft-disable strategy that iSeries already uses.
      
      This version renames paca->proc_enabled to paca->soft_enabled, and
      changes a couple of soft-disables in the kexec code to hard-disables,
      which should fix the crash that Michael Ellerman saw.  This doesn't
      yet use a reserved CR field for the soft_enabled and hard_enabled
      flags.  This applies on top of Stephen Rothwell's patches to make it
      possible to build a combined iSeries/other kernel.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d04c56f7
  16. 04 10月, 2006 1 次提交
  17. 02 10月, 2006 1 次提交
    • S
      [PATCH] namespaces: utsname: use init_utsname when appropriate · 96b644bd
      Serge E. Hallyn 提交于
      In some places, particularly drivers and __init code, the init utsns is the
      appropriate one to use.  This patch replaces those with a the init_utsname
      helper.
      
      Changes: Removed several uses of init_utsname().  Hope I picked all the
      	right ones in net/ipv4/ipconfig.c.  These are now changed to
      	utsname() (the per-process namespace utsname) in the previous
      	patch (2/7)
      
      [akpm@osdl.org: CIFS fix]
      Signed-off-by: NSerge E. Hallyn <serue@us.ibm.com>
      Cc: Kirill Korotaev <dev@openvz.org>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Herbert Poetzl <herbert@13thfloor.at>
      Cc: Andrey Savochkin <saw@sw.ru>
      Cc: Serge Hallyn <serue@us.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      96b644bd
  18. 01 10月, 2006 1 次提交
  19. 13 9月, 2006 1 次提交
  20. 31 7月, 2006 1 次提交
  21. 13 7月, 2006 1 次提交
  22. 03 7月, 2006 1 次提交
    • B
      [POWERPC] Add new interrupt mapping core and change platforms to use it · 0ebfff14
      Benjamin Herrenschmidt 提交于
      This adds the new irq remapper core and removes the old one.  Because
      there are some fundamental conflicts with the old code, like the value
      of NO_IRQ which I'm now setting to 0 (as per discussions with Linus),
      etc..., this commit also changes the relevant platform and driver code
      over to use the new remapper (so as not to cause difficulties later
      in bisecting).
      
      This patch removes the old pre-parsing of the open firmware interrupt
      tree along with all the bogus assumptions it made to try to renumber
      interrupts according to the platform. This is all to be handled by the
      new code now.
      
      For the pSeries XICS interrupt controller, a single remapper host is
      created for the whole machine regardless of how many interrupt
      presentation and source controllers are found, and it's set to match
      any device node that isn't a 8259.  That works fine on pSeries and
      avoids having to deal with some of the complexities of split source
      controllers vs. presentation controllers in the pSeries device trees.
      
      The powerpc i8259 PIC driver now always requests the legacy interrupt
      range. It also has the feature of being able to match any device node
      (including NULL) if passed no device node as an input. That will help
      porting over platforms with broken device-trees like Pegasos who don't
      have a proper interrupt tree.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      0ebfff14
  23. 01 7月, 2006 1 次提交
  24. 29 6月, 2006 1 次提交
    • M
      [POWERPC] Make sure smp_processor_id works very early in boot · 33dbcf72
      Michael Ellerman 提交于
      There's a small period early in boot where we don't know which cpu we're
      running on. That's ok, except that it means we have no paca, or more
      correctly that our paca pointer points somewhere random.
      
      So that we can safely call things like smp_processor_id(), we need a paca,
      so just assume we're on cpu 0. No code should _write_ to the paca before
      we've set the correct one up.
      
      We setup the proper paca after we've scanned the flat device tree in
      early_setup(), so there's no need to do it again in start_here_common.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      33dbcf72
  25. 28 6月, 2006 3 次提交
  26. 19 5月, 2006 4 次提交
  27. 05 5月, 2006 1 次提交
  28. 28 4月, 2006 1 次提交
  29. 02 4月, 2006 1 次提交