1. 20 3月, 2006 9 次提交
    • D
      [SPARC64]: Kill {save,restore}_alternate_globals() · 96c6e0d8
      David S. Miller 提交于
      No longer needed now that we no longer have hard-coded
      alternate global register usage.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      96c6e0d8
    • D
      b70c0fa1
    • D
      [SPARC64]: Dynamically grow TSB in response to RSS growth. · bd40791e
      David S. Miller 提交于
      As the RSS grows, grow the TSB in order to reduce the likelyhood
      of hash collisions and thus poor hit rates in the TSB.
      
      This definitely needs some serious tuning.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bd40791e
    • D
      [SPARC64]: Add infrastructure for dynamic TSB sizing. · 98c5584c
      David S. Miller 提交于
      This also cleans up tsb_context_switch().  The assembler
      routine is now __tsb_context_switch() and the former is
      an inline function that picks out the bits from the mm_struct
      and passes it into the assembler code as arguments.
      
      setup_tsb_parms() computes the locked TLB entry to map the
      TSB.  Later when we support using the physical address quad
      load instructions of Cheetah+ and later, we'll simply use
      the physical address for the TSB register value and set
      the map virtual and PTE both to zero.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      98c5584c
    • D
      [SPARC64]: TSB refinements. · 09f94287
      David S. Miller 提交于
      Move {init_new,destroy}_context() out of line.
      
      Do not put huge pages into the TSB, only base page size translations.
      There are some clever things we could do here, but for now let's be
      correct instead of fancy.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      09f94287
    • D
      [SPARC64]: Elminate all usage of hard-coded trap globals. · 56fb4df6
      David S. Miller 提交于
      UltraSPARC has special sets of global registers which are switched to
      for certain trap types.  There is one set for MMU related traps, one
      set of Interrupt Vector processing, and another set (called the
      Alternate globals) for all other trap types.
      
      For what seems like forever we've hard coded the values in some of
      these trap registers.  Some examples include:
      
      1) Interrupt Vector global %g6 holds current processors interrupt
         work struct where received interrupts are managed for IRQ handler
         dispatch.
      
      2) MMU global %g7 holds the base of the page tables of the currently
         active address space.
      
      3) Alternate global %g6 held the current_thread_info() value.
      
      Such hardcoding has resulted in some serious issues in many areas.
      There are some code sequences where having another register available
      would help clean up the implementation.  Taking traps such as
      cross-calls from the OBP firmware requires some trick code sequences
      wherein we have to save away and restore all of the special sets of
      global registers when we enter/exit OBP.
      
      We were also using the IMMU TSB register on SMP to hold the per-cpu
      area base address, which doesn't work any longer now that we actually
      use the TSB facility of the cpu.
      
      The implementation is pretty straight forward.  One tricky bit is
      getting the current processor ID as that is different on different cpu
      variants.  We use a stub with a fancy calling convention which we
      patch at boot time.  The calling convention is that the stub is
      branched to and the (PC - 4) to return to is in register %g1.  The cpu
      number is left in %g6.  This stub can be invoked by using the
      __GET_CPUID macro.
      
      We use an array of per-cpu trap state to store the current thread and
      physical address of the current address space's page tables.  The
      TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this
      table, it uses __GET_CPUID and also clobbers %g1.
      
      TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load
      the current processor's IRQ software state into %g6.  It also uses
      __GET_CPUID and clobbers %g1.
      
      Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the
      current address space's page tables into %g7, it clobbers %g1 and uses
      __GET_CPUID.
      
      Many refinements are possible, as well as some tuning, with this stuff
      in place.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      56fb4df6
    • D
      [SPARC64]: Kill pgtable quicklists and use SLAB. · 3c936465
      David S. Miller 提交于
      Taking a nod from the powerpc port.
      
      With the per-cpu caching of both the page allocator and SLAB, the
      pgtable quicklist scheme becomes relatively silly and primitive.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3c936465
    • D
      [SPARC64]: Move away from virtual page tables, part 1. · 74bf4312
      David S. Miller 提交于
      We now use the TSB hardware assist features of the UltraSPARC
      MMUs.
      
      SMP is currently knowingly broken, we need to find another place
      to store the per-cpu base pointers.  We hid them away in the TSB
      base register, and that obviously will not work any more :-)
      
      Another known broken case is non-8KB base page size.
      
      Also noticed that flush_tlb_all() is not referenced anywhere, only
      the internal __flush_tlb_all() (local cpu only) is used by the
      sparc64 port, so we can get rid of flush_tlb_all().
      
      The kernel gets it's own 8KB TSB (swapper_tsb) and each address space
      gets it's own private 8K TSB.  Later we can add code to dynamically
      increase the size of per-process TSB as the RSS grows.  An 8KB TSB is
      good enough for up to about a 4MB RSS, after which the TSB starts to
      incur many capacity and conflict misses.
      
      We even accumulate OBP translations into the kernel TSB.
      
      Another area for refinement is large page size support.  We could use
      a secondary address space TSB to handle those.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      74bf4312
    • B
      [SPARC64]: fix sparc_floppy_irq's auxio_register reseting · 94bbc176
      Bernhard R Link 提交于
      The patch "[SPARC64]: Get rid of fast IRQ feature"
      moved the the code from arch/sparc64/kernel/entry.S:
            lduba           [%g7] ASI_PHYS_BYPASS_EC_E, %g5
            or              %g5, AUXIO_AUX1_FTCNT, %g5
            stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
            andn            %g5, AUXIO_AUX1_FTCNT, %g5
            stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
      to arch/sparc64/kernel/irq.c:
                    val = readb(auxio_register);
                    val |= AUXIO_AUX1_FTCNT;
                    writeb(val, auxio_register);
                    val &= AUXIO_AUX1_FTCNT;
                    writeb(val, auxio_register);
      This looks like it it missing a bitwise not, which is reintroduced
      by this patch.
      
      Due to lack of a floppy device, I could not test it, but it looks
      evident.
      Signed-off-by: NBernhard R Link <brlink@debian.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      94bbc176
  2. 05 3月, 2006 1 次提交
  3. 27 2月, 2006 1 次提交
  4. 13 2月, 2006 1 次提交
  5. 10 2月, 2006 1 次提交
  6. 08 2月, 2006 1 次提交
  7. 30 1月, 2006 1 次提交
  8. 23 1月, 2006 1 次提交
  9. 20 1月, 2006 1 次提交
  10. 19 1月, 2006 4 次提交
    • D
      [SPARC]: Add support for *at(), ppoll, and pselect syscalls. · 2d7d5f05
      David S. Miller 提交于
      This also includes by necessity _TIF_RESTORE_SIGMASK support,
      which actually resulted in a lot of cleanups.
      
      The sparc signal handling code is quite a mess and I should
      clean it up some day.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2d7d5f05
    • U
      [PATCH] vfs: *at functions: core · 5590ff0d
      Ulrich Drepper 提交于
      Here is a series of patches which introduce in total 13 new system calls
      which take a file descriptor/filename pair instead of a single file
      name.  These functions, openat etc, have been discussed on numerous
      occasions.  They are needed to implement race-free filesystem traversal,
      they are necessary to implement a virtual per-thread current working
      directory (think multi-threaded backup software), etc.
      
      We have in glibc today implementations of the interfaces which use the
      /proc/self/fd magic.  But this code is rather expensive.  Here are some
      results (similar to what Jim Meyering posted before).
      
      The test creates a deep directory hierarchy on a tmpfs filesystem.  Then
      rm -fr is used to remove all directories.  Without syscall support I get
      this:
      
      real    0m31.921s
      user    0m0.688s
      sys     0m31.234s
      
      With syscall support the results are much better:
      
      real    0m20.699s
      user    0m0.536s
      sys     0m20.149s
      
      The interfaces are for obvious reasons currently not much used.  But they'll
      be used.  coreutils (and Jeff's posixutils) are already using them.
      Furthermore, code like ftw/fts in libc (maybe even glob) will also start using
      them.  I expect a patch to make follow soon.  Every program which is walking
      the filesystem tree will benefit.
      Signed-off-by: NUlrich Drepper <drepper@redhat.com>
      Signed-off-by: NAlexey Dobriyan <adobriyan@gmail.com>
      Cc: Christoph Hellwig <hch@lst.de>
      Cc: Al Viro <viro@ftp.linux.org.uk>
      Acked-by: NIngo Molnar <mingo@elte.hu>
      Cc: Michael Kerrisk <mtk-manpages@gmx.net>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      5590ff0d
    • D
      [SPARC64]: Fix build with CONFIG_COMPAT disabled. · 959a85ad
      David S. Miller 提交于
      Based upon a report and preliminary patch from Jim Gifford.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      959a85ad
    • E
      [SPARC64]: Serial Console for E250 Patch · c126cf80
      Eddie C. Dost 提交于
      From: Eddie C. Dost <ecd@brainaid.de>
      
      I have the following patch for serial console over the RSC
      (remote system controller) on my E250 machine. It basically adds
      support for input-device=rsc and output-device=rsc from OBP, and
      allows 115200,8,n,1,- serial mode setting.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      
      
      c126cf80
  11. 18 1月, 2006 1 次提交
    • R
      [SPARC64]: Eliminate race condition reading Hummingbird STICK register · 9eb3394b
      Richard Mortimer 提交于
      Ensure a consistent value is read from the STICK register by ensuring
      that both high and low are read without high changing due to a roll
      over of the low register.
      
      Various Debian/SPARC users (myself include) have noticed problems with
      Hummingbird based systems. The symptoms are that the system time is
      seen to jump forward 3 days, 6 hours, 11 minutes give or take a few
      seconds. In many cases the system then hangs some time afterwards.
      
      I've spotted a race condition in the code to read the STICK register.
      I could not work out why 3d, 6h, 11m is important but guess that it is
      due to the 2^32 jump of STICK (forwards on one read and then the next
      read will seem to be backwards) during a timer interrupt. I'm guessing
      that a change of -2^32 will get converted to a large unsigned
      increment after the arithmetic manipulation between STICK,
      nanoseconds, jiffies etc.
      
      I did a test where I modified __hbird_read_stick to artificially
      inject rollover faults forcefully every few seconds. With this I saw
      the clock jump over 6 times in 12 hours compared to once every month
      or so.
      Signed-off-by: NRichard Mortimer <richm@oldelvet.org.uk>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9eb3394b
  12. 13 1月, 2006 3 次提交
  13. 12 1月, 2006 2 次提交
  14. 11 1月, 2006 5 次提交
  15. 10 1月, 2006 4 次提交
  16. 09 1月, 2006 1 次提交
  17. 29 12月, 2005 1 次提交
  18. 23 12月, 2005 1 次提交
  19. 13 12月, 2005 1 次提交