The DMA FIFO threshold registers and burst size registers have changed
for OMAP4.  The current code only handles OMAP2/3 case, and so the
values are a bit off for OMAP4.  A summary of the differences between
OMAP2/3 and OMAP4:

Burst size:
OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits
OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits

Threshold size:
OMAP2/3: in bytes (8 bit units)
OMAP4: in 128bit units

This patch fixes the issue by creating two new helper functions in
dss_features: dss_feat_get_buffer_size_unit() and
dss_feat_get_burst_size_unit(). These return (in bytes) the unit size
for threshold registers and unit size for burst size register,
respectively, and are used to calculate correct values.

For the threshold size the usage is straightforward. However, the burst
size register has different multipliers for OMAP2/3 and OMAP4. This
patch solves the problem by defining the multipliers for the burst size
as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition
(i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist
on OMAP2/3 by defining the burst size unit as 64bit.

As the driver in practice always uses the maximum burst size, and no use
case currently exists where we would want to use a smaller burst size,
this patch changes the driver to hardcode the burst size when
initializing DISPC. This makes the threshold configuration code somewhat
simpler.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

When the panel driver calls omapdss_dsi_display_disable() it is possible
that there are still some unsent packets in the TX fifo.

Add dsi_sync_vc() calls in the beginning of
omapdss_dsi_display_disable() to make sure the TX fifos are empty.

This allows us to remove the msleep(10) hack from panel-taal.c
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

LANEx_ULPS_SIG2 bits are left on after entering ULPS. This doesn't cause
any problems currently, as DSI HW is reset when it is enabled. However,
if the reset is not done, operation fails if the bits are still set.

So reset the bits after entering ULPS to ensure operation even without
HW reset.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Using empty macros for performance measurement functions when DSS DEBUG
is not enabled causes an unused variable warning.

Change the empty macros to empty inline functions to remove the
warning.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The line buffer sizes vary across DSI modules, create a function
dsi_get_line_buf_size() using DSI_GNQ register to get the size of
line buffer used for the DISPC video port data.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

On OMAP3, the DSI module has 2 data lanes. On OMAP4, DSI1 has 4 data lanes
and DSI2 has 2 data lanes. Introduce function dsi_get_num_data_lanes() which
returns the number of data lanes on the dsi interface, introduce function
dsi_get_num_data_lanes_dssdev() which returns the number of data lanes used by
the omap_dss_device connected to the lanes.

Use the DSI_GNQ register on OMAP4 to get the number of data lanes, modify
dsi.c to use the number of lanes and the extra data lanes on DSI1.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

In the previous DSI driver design, a private workqueue was needed to prevent a
deadlock as explained in the commit : 0f16aa0a
. In the current design, the workqueue is only used for queueing delayed work in
the case where we don't get a FRAMEDONE interrupt for 250 milliseconds. It is
safe to remove the private workqueue amd use the system workqueue instead to
schedule the delayed work with the new design where the deadlock can't occur.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

dsi_dump_clocks() prints lck and pck rates for the DISPC channel which it is
connected to. Remove this since it is already printed by dispc_dump_clocks()
in debugfs.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Introduce DSI2 PLL clock sources needed by LCD2 channel and DSI2 Protocol
engine and DISPC Functional clock. Do the following:

- Modify dss_get_dsi_clk_source() and dss_select_dsi_clk_source() to take the
  dsi module number as an argument.
- Create debugfs files for dsi2, split the corresponding debugfs functions.
- Allow DPI to use these new clock sources.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

dsi_packet_sent_handler_vp() and dsi_packet_sent_handler_l4() currently
receive the completion parameter as their argument. This is not sufficient
information to differentiate between DSI1 and DSI2 platform devices.

Pass the struct "dsi_packet_sent_handler_data" to the packet_sent_handler
isrs, these contain the platform_device pointer of the DSI device and the
pointer to the completion struct.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The dsi related data structure currently creates one global instance of itself
which is accessed by dsi functions. Remove this global structure instance and
declare the struct as dsi_data. Modify dsi_init() to allocate a "dsi_data"
structure for each platform device instance. Link this data with the device's
platform_device pointer. Create the function dsi_get_dsidrv_data() which takes
the pdev and return a pointer to the device's dsi_data.

Make dsi_get_dsidev_id() return only 0 for now, this will be removed once the
name of the DSI platform device is changed to the device instance form, like
"omapdss_dsi.0" and "omapdss_dsi.1" etc.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The DSI interface is represented as a platform device, using the DSI platform
driver(dsi.c). The current DSI driver design is capable of running only one
instance of a DSI device. On OMAP4, there are 2 very similar DSI modules which
can be represented as instances of "omapdss_dsi" platform device.

Add member "module" in "dssdev.phy.dsi" that tells us which DSI module's lanes
the panel is connected to. Modify dsi.c functions to take the device's
platform_device struct pointer, provide functions dsi_get_dsidev_from_dssdev()
and dsi_get_dsidev_from_id() take the panel's omap_dss_device and module number
respectively, and return the platform_device pointer. Currently, the dsi struct
is declared globally and is accessed when dsi data is needed. The new pdev
argument will be used later to provide the platform device's dsi related data.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The function dsi_pll_init() has omap_dss_device argument which is
not used. Remove this argument.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add pointer to omap_dss_device struct as an argument in the functions which
are exported to dsi panel drivers. This argument will tell the DSI driver
which DSI interface's data it has to choose.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

OMAP4 requires SCP clocks enabled to access DSI PLL registers and DSI COMPLEXIO
registers. Enable scp clock before accessing the registers and disable it before
exiting dsi_dump_regs().
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

OMAP4 DSI block has new interrupts for the two new DSI lanes.

Add definitions for those interrupts, and add the interrupts to the CIO
error mask.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The panel drivers can leave the VDDS_DSI regulator enabled, even when
the panel is disabled, to ensure that the DSI pins are powered.

This patch ensures that VDDS_DSI is disabled on DSI module unload.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add dsi_mux_pads function pointer to omap_dss_board_info, and use the
function pointer in DSI code to configure the DSI pads either to normal
DSI operation, or to pull down when in ULPS.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add parameter to omapdss_dsi_display_disable() which the panel driver
can use to tell if the DSI lanes should be put to ULPS before disabling
the interface.

This can be used to skip ULPS entry in cases where the panel doesn't
care about ULPS state, for example when the panel will be reset, or when
the display interface will be enabled again right after the disable.

This will speed up the operation considerably in cases where entering
ULPS would fail with timeout, and the panel driver isn't even interested
in entering ULPS.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add dsi_cio_wait_tx_clk_esc_reset() function which waits for the
TXCLKESC domains to come out of reset.

Things have worked fine without this, but better be safe than sorry.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Use dsi_enable_scp_clk and dsi_disable_scp_clk in CIO init and uninit,
and improve the CIO init by adding a few status checks and error
handling.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

SCP clock is needed for CIO on OMAP3, and for CIO and PLL on OMAP4.
Current driver enables the CIO clock always when DSI display is
initialized. However, if a DPI display tries to use DSI PLL, the SCP
clock is never enabled.

This patch implements simple ref counting enable/disable functions for
SCP clock.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The bits for TXCLKESCx reset have changed for OMAP3630 and OMAP4.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Rename ComplexIO from dsi_complexio_xxx to dsi_cio_xxx for brevity.
Also, add cio prefix for couple of functions that didn't have it, but
are cio related.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The DSI pins are powered by VDDS_DSI. If VDDS_DSI is off, the DSI pins
are floating even if they are pinmuxed to, say, safe mode and there's a
pull down/up.

This patch gives the panel drivers an option to leave the VDDS_DSI power
enabled while the DSS itself is turned off. This can be used to keep the
DSI lanes in a valid state while DSS is off, if the DSI pins are muxed
for pull down (not done in this patch).

There will be a slight power consumption increase (~100 uA?) when the
VDDS_DSI is left on, but because this option is used when the panel is
left on, the regulator consumption is negligible compared to panel power
consumption.

When the panel is fully turned off the VDDS_DSI is also turned off.

As an added bonus this will give us faster start up time when starting
up the DSS and the regulator is already enabled.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Entering ULPS (Ultra Low Power State) happens by sending ULPS entry
sequence to the DSI peripheral and pulling the DSI lines down.

Exiting ULPS happens by sending ULPS exit sequence.

We can send the ULPS entry sequence by using OMAP DSS HW's ULPS support,
but we cannot use the ULPS exit support from DSS HW. DSS HW refuses to
send the ULPS exit sequence if it thinks that the lanes are not in ULPS.
After being in OFF mode the DSS HW has been reset, and so it does not
know that the lanes are actually in ULPS.

Thus we need to use the lane override support and manually send the ULPS
exit sequence. Luckily the sequence is very simple.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

CIO LDO status check seems to be broken on OMAP3630+ chips, and it's
also quite unclear what LDO status actually tells and when its status
changes.

This patch removes the whole check on the grounds that if there's a
problem with the LDO, we should anyway catch the problem as we check the
CIO power state and CIO reset status.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DSI_DSIPHY_CFG10 register can be used to override DSI lane state. Add
functions to configure and enable the override, and to disable the
override.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The clock sources for DISPC_FCLK and LCD1_CLK are now specified in the board file.
There is no need for the hack config "CONFIG_OMAP2_DSS_USE_DSI_PLL" anymore.
Introduce function dpi_use_dsi_pll() which checks for the clock sources to decide
whether DSI PLL is to be used or not.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add enum dss_clock_source in dssdev.clocks struct so that the clock sources can
be specified in the board file.
Replace hard coded clock sources in dsi.c, dpi.c and replace them with the new
clock source members in dssdev.clocks. Modify the sdp4430_lcd_device struct in
board-4430sdp.c to specify clock sources for DISPC_FCLK, LCD1_CLK and DSI1_FCLK.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Change enum dss_clk_source to omap_dss_clock_source and move it to
'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning.
These changes are done in order to specify the clock sources for DSS in the
board file.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Clock configuration was defined inside dssdev.phy.dsi struct. The clock
config doesn't really belong there, and so it's moved to dssdev.clock
struct.

Now the explicit clock configuration could also be used for other
interfaces than DSI, although there's no support for it currently.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The DSI protocol engine has no interrupt for signalling the end of a Frame
transfer. The present approach is to send a BTA after DISPC generates a
FRAMEDONE interrupt, and unlock the dsi bus only when the BTA Ack is received.

The assumption made with this approach was that OMAP will send a BTA only after
the long packet corresponding to the last line is sent. However, it is possible
that on the DISPC FRAMEDONE interrupt there are 2 (or more) lines of pixel data
in the DSI line buffer. Hence, the BTA Ack could be received for the long packet
corresponding to the second last line (or the third last and so on..).
Therefore, the current method doesn't ensure that the complete frame data is
sent before we start a new transfer. A similar explanation holds valid if we
send a BTA in between multiple short/long command packets from the slave port.

Introduce dsi_sync_vc functions, based on Tomi Valkeinen's idea, which ensure
that the DSI Virtual Channel in use(update_channel) completes its previous work
before proceeding to the next Frame/Command.

For a frame update, the DSI driver now sends a callback to the Panel Driver
on the FRAMEDONE interrupt itself. The callback in the panel driver then unlocks
the bus. dsi_sync_vc() functions are placed in dsi_vc_config_l4() and
dsi_vc_config_vp() to ensure that the previous task of the Virtual Channel is
completed.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The following changes have changed from OMAP3 to OMAP4 DSI:
-The register field DSI_PLL_FREQSEL in DSI_PLL_CONFIGURATION2 has been removed.
-DCS_CMD_ENABLE and DCS_CMD_CODE bits have been moved from DSI_CTRL to
DSI_VC_CTRLi, hence the control of the bits is available per VC.
-DSI LDO powergood notification doesn't work on OMAP4. This is mentioned in
OMAP4 errata revision 1.8(Errata 1.76).
-OCP_WIDTH register field is included in DSI_VC_CTRL.
-The SCP clock is also required to access DSI PLL registers

Introduce dss features for these changes so that DSI runs on both OMAP3 and
OMAP4.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3)
to not work properly. The bug prevents us from enabling DSI PLL power
only to HS divider block.

This patch adds a dss feature for the bug and converts POWER_ON_DIV
requests to POWER_ON_ALL (0x2).
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

On OMAP4, reading DSI_PLL_CONFIGURATION2 register requires the L3 clock
(CIO_CLK_ICG) to PLL. Currently dsi_dump_clocks() tries to read that
register without enabling the L3 clock, leading to crash if DSI is not
in use.

The status of the bit being read from DSI_PLL_CONFIGURATION2 is
available from dsi_clock_info->use_sys_clk, so we can avoid the whole
problem by just using that.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

use_sys_clk and highfreq fields in dsi.current_cinfo were never set.
Luckily they weren't used anywhere so it didn't cause any problems.

This patch fixes those fields and they are now set at the same time as
the rest of the fields.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

arch/arm/plat-omap/include/plat/display.h is an include for the OMAP DSS
driver. A more logical place for it is in include/video.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3)
to not work properly. The bug prevents us from enabling DSI PLL power
only to HS divider block.

This patch adds a dss feature for the bug and converts POWER_ON_DIV
requests to POWER_ON_ALL (0x2).
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

On OMAP4, reading DSI_PLL_CONFIGURATION2 register requires the L3 clock
(CIO_CLK_ICG) to PLL. Currently dsi_dump_clocks() tries to read that
register without enabling the L3 clock, leading to crash if DSI is not
in use.

The status of the bit being read from DSI_PLL_CONFIGURATION2 is
available from dsi_clock_info->use_sys_clk, so we can avoid the whole
problem by just using that.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>