- 05 9月, 2012 1 次提交
-
-
由 Philip Rakity 提交于
On some systems the host controller does not support vccq signaling. This is supplied by a dedicated regulator (vqmmc). Add support for this regulator. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 23 7月, 2012 2 次提交
-
-
由 Aaron Lu 提交于
Add a new flag of SDHCI_USING_RETUNING_TIMER to represent if the host is using a retuning timer for the card inserted. This flag is set when the host does tuning the first time for the card and the host's retuning mode is 1. This flag is used afterwards whenever needs to decide if the host is currently using a retuning timer. This flag is cleared when the card is removed in sdhci_reinit. The set/clear of the flag and the start/stop of the retuning timer is associated with the card's init/remove time, so there is no need to touch it when the host is to be removed as at that time the card should have already been removed. Signed-off-by: NAaron Lu <aaron.lu@amd.com> Reviewed-by: NGirish K S <girish.shivananjappa@linaro.org> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Philip Rakity 提交于
Currently only the capability_0 register can be set if SDHCI_QUIRK_MISSING_CAPS is defined. This is a problem when the capability_1 register also needs changing. Use the quirk SDHCI_QUIRK_MISSING_CAPS to allow both registers to be set. Redefining caps[1] is useful when the board design does not support 1.8v vccq so UHS modes are not available. The code that calls sdhci_add_host can then detect this condition and adjust the caps so the UHS mode will not be attempted on UHS cards. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 06 4月, 2012 2 次提交
-
-
由 Chris Ball 提交于
This reverts commit c16e981b2fd9455af670a69a84f4c8cf07e12658, because it's no longer useful once MSI support is reverted. Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Manuel Lauss 提交于
MSI on my O2Micro OZ600 SD card reader is broken. This patch adds a quirk to disable MSI on these controllers. Signed-off-by: NManuel Lauss <manuel.lauss@googlemail.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 28 3月, 2012 1 次提交
-
-
由 Adrian Hunter 提交于
Add quirk SDHCI_QUIRK2_HOST_OFF_CARD_ON to cater for the case when the card keeps power during suspend but the host controller does not i.e. the card power is not controlled by the host controller. In that case, the controller must be fully reset on resume. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 13 1月, 2012 1 次提交
-
-
由 Girish K S 提交于
This patch adds support for the HS200 mode on the host side. Also enables the tuning feature required when the HS200 mode is selected. Signed-off-by: NGirish K S <girish.shivananjappa@linaro.org> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 12 1月, 2012 1 次提交
-
-
由 Adrian Hunter 提交于
Even if a driver provides separate card detection, an interrupt is still needed to abort mmc requests that are in progress. SDHCI_QUIRK2_OWN_CARD_DETECTION prevents that, so remove it. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 27 10月, 2011 1 次提交
-
-
由 Adrian Hunter 提交于
Ths patch allows runtime PM for sdhci-pci, runtime suspending after inactivity of 50ms and ensuring runtime resume before SDHC registers are accessed. During runtime suspend, interrupts are masked. The host controller state is restored at runtime resume. For Medfield, the host controller's card detect mechanism is supplanted by an always-on GPIO which provides for card detect wake-up. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 21 7月, 2011 1 次提交
-
-
由 Robert P. J. Day 提交于
Standardize the checks for multiple MMC header file inclusion, including adding comments to terminating #endif's, and fixing one incorrect comment. Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 26 5月, 2011 2 次提交
-
-
由 Andrei Warkentin 提交于
Enables Auto-CMD23 support where available (SDHCI 3.0 controllers) Signed-off-by: NAndrei Warkentin <andreiw@motorola.com> Tested-by: NArindam Nath <arindam.nath@amd.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Andrei Warkentin 提交于
Implements support for multiblock transfers bounded by SET_BLOCK_COUNT (CMD23). Signed-off-by: NAndrei Warkentin <andreiw@motorola.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 25 5月, 2011 4 次提交
-
-
由 Arindam Nath 提交于
Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Arindam Nath 提交于
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Arindam Nath 提交于
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Takashi Iwai 提交于
On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by: NTakashi Iwai <tiwai@suse.de> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 09 1月, 2011 2 次提交
-
-
由 Olof Johansson 提交于
Some controllers misparse segment length 0 as being 0, not 65536. Add a quirk to deal with it. Signed-off-by: NOlof Johansson <olof@lixom.net> Reviewed-by: NChris Ball <cjb@laptop.org> Signed-off-by: NChris Ball <cjb@laptop.org>
-
由 Takashi Iwai 提交于
JMicron 388 SD/MMC combo controller supports the 1.8V low-voltage for SD, but MMC doesn't work with the low-voltage, resulting in an error at probing. This patch adds the support for multiple voltage mask per device type, so that SD works with 1.8V while MMC forces 3.3V. Here new ocr_avail_* fields for each device are introduced, so that the actual OCR mask is switched dynamically. Also, the restriction of low-voltage in core/sd.c is removed when the bit is allowed explicitly via ocr_avail_sd mask. This patch was rewritten from scratch based on Aries' original code. Signed-off-by: NAries Lee <arieslee@jmicron.com> Signed-off-by: NTakashi Iwai <tiwai@suse.de> Reviewed-by: NChris Ball <cjb@laptop.org> Signed-off-by: NChris Ball <cjb@laptop.org>
-
- 23 10月, 2010 1 次提交
-
-
由 Giuseppe Cavallaro 提交于
Some platforms based on sdhci-pltfm need to set their own quirks. Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h. This patch splits drivers/mmc/host/sdhci.h into two parts: * drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors. * include/linux/mmc/sdhci.h includes the sdhci structure and quirks. Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h. This patch avoids adding/changing the calls/flags in the sdhci_pltfm_data structure. It has been tested on STM platforms (e.g. STx7106, STx7108, STx5206) where the driver is configured and used as shown in the example below: [snip] static int mmc_pad_resources(struct sdhci_host *sdhci) { if (!devm_stm_pad_claim(sdhci->mmc->parent, &stx7108_mmc_pad_config, dev_name(sdhci->mmc->parent))) return -ENODEV; return 0; } static struct sdhci_pltfm_data stx7108_mmc_platform_data = { .init = mmc_pad_resources, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; static struct platform_device stx7108_mmc_device = { .name = "sdhci", [snip] Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h, and no modifications should be needed on other sdhci-<XXX> drivers. Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NChris Ball <cjb@laptop.org>
-