In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This matters to any sort of device that is wired to one of the CPU
interrupt pins on an SMP system.  Typically the scenario is most easily
triggered with the count/compare timer interrupt where the same interrupt
number and thus irq_desc is used on each processor.

   CPU A			CPU B

   do_IRQ()
   generic_handle_irq()
   handle_level_irq()
   spin_lock(desc_lock)
   set IRQ_INPROGRESS
   spin_unlock(desc_lock)
				do_IRQ()
				generic_handle_irq()
				handle_level_irq()
				spin_lock(desc_lock)
				IRQ_INPROGRESS set => bail out
   spin_lock(desc_lock)
   clear IRQ_INPROGRESS
   spin_unlock(desc_lock)

In case of the cp0 compare interrupt this means the interrupt will be
acked and not handled or re-armed on CPU b, so there won't be any timer
interrupt until the count register wraps around.

With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just
working right on VSMP because the count registers are synchronized on
bootup so it takes something that disables interrupts for a long time on
one processor to trigger this one.

For scenarios where an interrupt is multicasted or broadcasted over several
CPUs the existing code was safe and the fix will break it.  There is no
way to know in the interrupt controller code because it is abstracted from
the platform code.  I think we do not have such a setup currently, so this
should be ok.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Adds a JR.HB after halting a TC, to ensure that the TC has really halted.
only modifies the TCSTATUS register when the TC is safely halted.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

We have no guarantee by the generic time code that the timer is stopped
when the ->next_event method is called.  Modifying the Timer Initial Count
register while the timer is enabled has UNPREDICTABLE effect according to
the BCM1250/BCM1125/BCM1125H User Manual.  So stop the timer before
reprogramming.

This is a paranoia fix; no ill effects have been observed previously.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For the old minimum of a single tick a value of zero would be programmed
into the init value register which in the BCM1250/BCM1125/BCM1125H User
Manual in the Timer Special Cases section is documented to have
UNPREDICTABLE effect.

Observable sympthoms of this bug were hangs of several seconds on the
console during bootup and later if both dyntick and highres timer options
were activated.

In theory contiguous mode of the timers is also affected but in an act of
hopeless lack of realism I'll assume nobody will ever configure a KERNEL
for HZ > 500kHz but if so I leave that to evolution to sort out.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Or strange things will happen.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

[akpm@linux-foundation.org: coding-style cleanups]
Signed-off-by: NRoel Kluin <12o3l@tiscali.nl>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The Jazz machines have to use the PIT timer for dyntick and highresolution
kernels.  This may break because currently just like i386 used to do MIPS
uses two separate spinlocks in the actual PIT code and the PC speaker
code.  So switch to do it the same that x86 currently does PIT locking.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* Do not include unnecessary headers.
* Do not mention time.README.
* Do not mention mips_timer_ack.
* Make clocksource_mips static.  It is now dedicated to c0_timer.
* Initialize clocksource_mips.read statically.
* Remove null_hpt_read.
* Remove an argument of plat_timer_setup.  It is just a placeholder.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

A comment on ptrace_getregs() states "Registers are sign extended to
fill the available space." but it is not true.  Fix code to match the
comment.  Also fix casts on each caller to get rid of some warnings.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Mmap with MAP_FIXED was not validating the addr and len parameters.  This
leads to the failure of GCC's gcc.c-torture/execute/loop-2[fg].c testcases
when using the o32 ABI on a 64 bit kernel.

These testcases try to mmap 65536 bytes at 0x7fff8000 and then access all
the memory.  In 2.6.18 and 2.6.23.1 (and likely other versions as well)
the kernel maps the requested memory, but since half of it is above
0x80000000 a SIGBUS is generated when it is accessed.

This patch moves the len validation above the MAP_FIXED processing so that
it is always validated.  It also adds validation to the addr parameter for
MAP_FIXED mappings.
Signed-off-by: NDavid Daney  <ddaney@avtrex.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Based on original patch by Roel Kluin <12o3l@tiscali.nl>.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

plat_timer_setup is no longer getting called.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Try increasingly longer time periods starting of at 0x10 cycles.  This
should be fast on hardware and work nicely with emulators.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The expression "(long)(read_c0_count() - cnt)" can never be a negative
value on 64-bit kernel.  Cast to "int" before comparison.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Convert jmr3927_clock_event_device to more generic
txx9tmr_clock_event_device which supports one-shot mode.  The
txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer
interrupt was not available.

Convert jmr3927_hpt_read to txx9_clocksource driver which does not
depends jiffies anymore.  The txx9_clocksource itself can be used for
TX49, but normally TX49 uses higher precision clocksource_mips.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This subtle difference makes ELF overlays work.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

clockevent_delta2ns() use the shift and mult value, so
clockevent_set_clock() should be called first.
Pointed out by Atsushi Nemoto.
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

set_next_event() and set_mode() are always called with interrupt disabled.
irqsave and irqrestore are not necessary for spinlock.
Pointed out by Atsushi Nemoto.
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Modify the SMTC initialization code to allow boot-time specification not
only of how many VPEs and TCs to use, but also how many TCs out of the
allowed pool are to be bound to VPE 0.  The new boot option is "vpe0tcs=N",
where N is an integer.  Using it in combination with the existing options
allows arbitrary assignments across the 2 VPEs of a 34K.  e.g. "maxtcs=3
 vpe0tcs=1" forces VPE0 to have 1 TC, while VPE1 has 2, and "maxtcs=4
vpe0tcs=3" forces VPE0 to have 3 TCs, while VPE1 gets 1.  If no vpe0tcs
option is specified, the traditional algorithm of evenly dividing TCs
between available VPEs, with the odd "slop" going to VPE0, is retained.

The reason for doing this is to allow a finer balancing of TCs which can
handle I/O interrupts on Malta (those on VPE 0) and those which cannot.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use write_c0_compare(read_c0_count()) to clear interrupt.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

And make use of it for Cobalt.  A few others such as the Malta could make
use of it as well.
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Fix the various misspellings of "system", controller", "interrupt" and
"[un]necessary".
Signed-off-by: NRobert P. J. Day <rpjday@mindspring.com>
Signed-off-by: NAdrian Bunk <bunk@kernel.org>

One of the easiest things to isolate is the pid printed in kernel log.
There was a patch, that made this for arch-independent code, this one makes
so for arch/xxx files.

It took some time to cross-compile it, but hopefully these are all the
printks in arch code.
Signed-off-by: NAlexey Dobriyan <adobriyan@openvz.org>
Signed-off-by: NPavel Emelyanov <xemul@openvz.org>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The set of functions process_session, task_session, process_group and
task_pgrp is confusing, as the names can be mixed with each other when looking
at the code for a long time.

The proposals are to
* equip the functions that return the integer with _nr suffix to
  represent that fact,
* and to make all functions work with task (not process) by making
  the common prefix of the same name.

For monotony the routines signal_session() and set_signal_session() are
replaced with task_session_nr() and set_task_session(), especially since they
are only used with the explicit task->signal dereference.
Signed-off-by: NPavel Emelianov <xemul@openvz.org>
Acked-by: NSerge E. Hallyn <serue@us.ibm.com>
Cc: Kirill Korotaev <dev@openvz.org>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Cedric Le Goater <clg@fr.ibm.com>
Cc: Herbert Poetzl <herbert@13thfloor.at>
Cc: Sukadev Bhattiprolu <sukadev@us.ibm.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>