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  1. 07 9月, 2012 7 次提交
    • P
      ARM: tegra: Port tegra to generic clock framework · 92fe58f0
      由 Prashant Gaikwad 提交于 
      This patch converts tegra clock code to generic clock framework in following way:
 - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c)
 - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk.
 - Initialize all clock data statically. (tegraXX_clocks_data.c)

Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions.
Removed init function. It's functionality is splitted into recalc_rate and is_enabled.

Static initialization is used since slab is not up in .init_early and clock
is needed to be initialized before clockevent/clocksource initialization.
Macros redefined for clk_tegra.

Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This
is to move quickly to generic common clock framework so that other dependent features will
not be blocked (such as DT binding).

Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20
and Tegra30.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      92fe58f0
    • P
      ARM: tegra: Add clk_tegra structure and helper functions · 96a1bd1e
      由 Prashant Gaikwad 提交于 
      Add Tegra platform specific clock structure clk_tegra and
some helper functions for generic clock framework.

struct clk_tegra is the single strcture used for all types of
clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      96a1bd1e
    • P
      ARM: tegra: Rename tegra20 clock file · 23fc5b24
      由 Prashant Gaikwad 提交于 
      Make the name consistent with other files.
s/tegra2/tegra20
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      23fc5b24
    • P
      ARM: tegra20: Separate out clk ops and clk data · 86edb87a
      由 Prashant Gaikwad 提交于 
      Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      86edb87a
    • P
      ARM: tegra30: Separate out clk ops and clk data · 88e790a4
      由 Prashant Gaikwad 提交于 
      Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      88e790a4
    • S
      ARM: tegra: fix U16 divider range check · eb70e1bd
      由 Stephen Warren 提交于 
      A U16 divider can divide a clock by 1..64K. However, the range-check
in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
downstream kernels already have the fixed range-check.

In practice this is a problem on Whistler's I2C bus, which uses a bus
clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
leading to a desired divider of 270. Prior to conversion to the common
clock framework, this range error was somehow ignored/irrelevant and
caused no problems. However, the common clock framework evidently has
more rigorous error-checking, so this failure causes the I2C bus to fail
to operate correctly.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      eb70e1bd
    • S
      ARM: tegra: turn on UART A clock at boot · 37c241ed
      由 Stephen Warren 提交于 
      Some boards use UART D for the main serial console, and some use UART A.
UART D's clock is listed in board-dt-tegra20.c's clock table, whereas
UART A's clock is not. This causes the clock code to think UART A's
clock is unsed. The common clock framework turns off unused clocks at
boot time. This makes the kernel appear to hang. Add UART A's clock into
the clock table to prevent this. Eventually, this requirement should be
handled by the UART driver, and/or properties in a board-specific device
tree file.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      37c241ed
  3. 02 9月, 2012 2 次提交
    • L
      Linux 3.6-rc4 · 4cbe5a55
      由 Linus Torvalds 提交于
      4cbe5a55
    • J
      time: Move ktime_t overflow checking into timespec_valid_strict · cee58483
      由 John Stultz 提交于 
      Andreas Bombe reported that the added ktime_t overflow checking added to
timespec_valid in commit 4e8b1452 ("time: Improve sanity checking of
timekeeping inputs") was causing problems with X.org because it caused
timeouts larger then KTIME_T to be invalid.

Previously, these large timeouts would be clamped to KTIME_MAX and would
never expire, which is valid.

This patch splits the ktime_t overflow checking into a new
timespec_valid_strict function, and converts the timekeeping codes
internal checking to use this more strict function.
Reported-and-tested-by: NAndreas Bombe <aeb@debian.org>
Cc: Zhouping Liu <zliu@redhat.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      cee58483
  5. 01 9月, 2012 3 次提交
  7. 31 8月, 2012 1 次提交
    • L
      Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux · 155e36d4
      由 Linus Torvalds 提交于 
      Pull drm fixes from Dave Airlie:
 "A bunch of scattered fixes ati/intel/nouveau, couple of core ones,
  nothing too shocking or different."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222S
  gma500: Consider CRTC initially active.
  drm/radeon: fix dig encoder selection on DCE61
  drm/radeon: fix double free in radeon_gpu_reset
  drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740
  drm/radeon: rework panel mode setup
  drm/radeon/atom: powergating fixes for DCE6
  drm/radeon/atom: rework DIG modesetting on DCE3+
  drm/radeon: don't disable plls that are in use by other crtcs
  drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700
  drm/radeon: initialize tracked CS state
  drm/radeon: fix reading CB_COLORn_MASK from the CS
  drm/nvc0/copy: check PUNITS to determine which copy engines are disabled
  i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard
  drm/i915: Use the correct size of the GTT for placing the per-process entries
  drm: Check for invalid cursor flags
  drm: Initialize object type when using DRM_MODE() macro
  drm/i915: fix color order for BGR formats on IVB
  drm/i915: fix wrong order of parameters in port checking functions
      155e36d4
  9. 30 8月, 2012 17 次提交
  11. 29 8月, 2012 10 次提交