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  1. 09 8月, 2013 1 次提交
  3. 21 6月, 2013 1 次提交
    • H
      clk: add support for Rockchip gate clocks · 646572c7
      由 Heiko Stübner 提交于 
      This adds basic support for gate-clocks on Rockchip SoCs.
There are 16 gates in each register and use the HIWORD_MASK
mechanism for changing gate settings.

The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all 160 gates can be put into
one gate clock spanning all registers or they can be divided into
the 10 individual gates containing 16 clocks each.
The code supports both approaches.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      646572c7
  5. 20 6月, 2013 1 次提交
  7. 01 6月, 2013 1 次提交
  9. 29 5月, 2013 1 次提交
  11. 27 5月, 2013 1 次提交
  13. 13 4月, 2013 1 次提交
  15. 27 3月, 2013 2 次提交
    • E
      clk: arm: sunxi: Add a new clock driver for sunxi SOCs · e874a669
      由 Emilio López 提交于 
      This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.

Additionally, document the new bindings introduced by this patch.

Idling:
    / # cat /sys/kernel/debug/clk/clk_summary
       clock                        enable_cnt  prepare_cnt  rate
    ---------------------------------------------------------------------
     osc32k                         0           0            32768
     osc24M_fixed                   0           0            24000000
        osc24M                      0           0            24000000
           apb1_mux                 0           0            24000000
              apb1                  0           0            24000000
           pll1                     0           0            60000000
              cpu                   0           0            60000000
                 axi                0           0            60000000
                    ahb             0           0            60000000
                       apb0         0           0            30000000
     dummy                          0           0            0

After "yes >/dev/null &":
    / # cat /sys/kernel/debug/clk/clk_summary
       clock                        enable_cnt  prepare_cnt  rate
    ---------------------------------------------------------------------
     osc32k                         0           0            32768
     osc24M_fixed                   0           0            24000000
        osc24M                      0           0            24000000
           apb1_mux                 0           0            24000000
              apb1                  0           0            24000000
           pll1                     0           0            1008000000
              cpu                   0           0            1008000000
                 axi                0           0            336000000
                    ahb             0           0            168000000
                       apb0         0           0            84000000
     dummy                          0           0            0
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      e874a669
    • P
      clk: Add composite clock type · ece70094
      由 Prashant Gaikwad 提交于 
      Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      ece70094
  17. 25 3月, 2013 1 次提交
  19. 20 3月, 2013 1 次提交
  21. 15 2月, 2013 1 次提交
    • A
      clk: sunxi: remove stale Makefile entry · fde8bc59
      由 Arnd Bergmann 提交于 
      Patch 85a18198 "clk: sunxi: Use common of_clk_init() function"
removed the clk-sunxi.c file but left the Makefile entry, which
causes a build error in multi_v7_defconfig:

make[4]: *** No rule to make target `drivers/clk/clk-sunxi.o', needed by `drivers/clk/built-in.o'.

The obvious fix is to remove the extraneous line from the
Makefile.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Maxime Ripard <maxime.ripard@anandra.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      fde8bc59
  23. 29 1月, 2013 1 次提交
    • P
      clk: tegra: add Tegra specific clocks · 8f8f484b
      由 Prashant Gaikwad 提交于 
      Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
      8f8f484b
  25. 24 1月, 2013 1 次提交
  27. 19 1月, 2013 1 次提交
  29. 20 11月, 2012 1 次提交
  31. 17 11月, 2012 1 次提交
  33. 14 11月, 2012 1 次提交
  35. 30 10月, 2012 1 次提交
  37. 21 9月, 2012 1 次提交
  39. 20 9月, 2012 1 次提交
  41. 16 9月, 2012 1 次提交
  43. 07 9月, 2012 2 次提交
  45. 01 9月, 2012 1 次提交
  47. 29 8月, 2012 1 次提交
  49. 25 8月, 2012 2 次提交
  51. 19 7月, 2012 1 次提交
  53. 12 7月, 2012 4 次提交
    • R
      clk: add highbank clock support · 8d4d9f52
      由 Rob Herring 提交于 
      This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
[mturquette@linaro.org: fixed up invalid writes to const struct member]
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      8d4d9f52
    • L
      clk: add versatile ICST307 driver · 91b87a47
      由 Linus Walleij 提交于 
      The ICST307 VCO clock has a shared driver in the ARM
architecture. This patch provides a wrapper into the common
clock framework so we can use the implementation in the
ARM architecture without duplicating the code until all
ARM platforms using this VCO are moved over. At that point
we can merge the driver from the ARM platform into the
generic file altogether.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: removed versatile Kconfig]
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      91b87a47
    • L
      ARM: u300: convert to common clock · 50667d63
      由 Linus Walleij 提交于 
      This converts the U300 clock implementation over to use the common
struct clk and moves the implementation down into drivers/clk.
Since VCO isn't used in tree it was removed, it's not hard to
put it back in if need be.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: trivial Makefile conflict]
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      50667d63
    • M
      clk: wm831x: Add initial WM831x clock driver · f05259a6
      由 Mark Brown 提交于 
      The WM831x and WM832x series of PMICs contain a flexible clocking
subsystem intended to provide always on and system core clocks.  It
features:

- A 32.768kHz crystal oscillator which can optionally be used to pass
  through an externally generated clock.
- A FLL which can be clocked from either the 32.768kHz oscillator or
  the CLKIN pin.
- A CLKOUT pin which can bring out either the oscillator or the FLL
  output.
- The 32.768kHz clock can also optionally be brought out on the GPIO
  pins of the device.

This driver fully supports the 32.768kHz oscillator and CLKOUT.  The FLL
is supported only in AUTO mode, the full flexibility of the FLL cannot
currently be used.

Due to a lack of access to systems where the core SoC has been converted
to use the generic clock API this driver has been compile tested only.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      f05259a6
  55. 11 6月, 2012 1 次提交
  57. 13 5月, 2012 1 次提交
    • V
      SPEAr: clk: Add VCO-PLL Synthesizer clock · 55b8fd4f
      由 Viresh Kumar 提交于 
      All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
      55b8fd4f
  59. 09 5月, 2012 2 次提交
  61. 17 3月, 2012 2 次提交
    • M
      clk: basic clock hardware types · 9d9f78ed
      由 Mike Turquette 提交于 
      Many platforms support simple gateable clocks, fixed-rate clocks,
adjustable divider clocks and multi-parent multiplexer clocks.

This patch introduces basic clock types for the above-mentioned hardware
which share some common characteristics.

Based on original work by Jeremy Kerr and contribution by Jamie Iles.
Dividers and multiplexor clocks originally contributed by Richard Zhao &
Sascha Hauer.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NMike Turquette <mturquette@ti.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      9d9f78ed
    • M
      clk: introduce the common clock framework · b2476490
      由 Mike Turquette 提交于 
      The common clock framework defines a common struct clk useful across
most platforms as well as an implementation of the clk api that drivers
can use safely for managing clocks.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

This patch introduces the common struct clk, struct clk_ops and an
implementation of the well-known clock api in include/clk/clk.h.
Platforms may define their own hardware-specific clock structure and
their own clock operation callbacks, so long as it wraps an instance of
struct clk_hw.

See Documentation/clk.txt for more details.

This patch is based on the work of Jeremy Kerr, which in turn was based
on the work of Ben Herrenschmidt.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NMike Turquette <mturquette@ti.com>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Reviewed-by: Rob Herring <rob.herring <at> calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      b2476490
  63. 26 11月, 2010 1 次提交