1. 12 7月, 2011 1 次提交
  2. 20 5月, 2011 1 次提交
  3. 04 5月, 2011 2 次提交
    • P
      powerpc: Save Come-From Address Register (CFAR) in exception frame · 48404f2e
      Paul Mackerras 提交于
      Recent 64-bit server processors (POWER6 and POWER7) have a "Come-From
      Address Register" (CFAR), that records the address of the most recent
      branch or rfid (return from interrupt) instruction for debugging purposes.
      
      This saves the value of the CFAR in the exception entry code and stores
      it in the exception frame.  We also make xmon print the CFAR value in
      its register dump code.
      
      Rather than extend the pt_regs struct at this time, we steal the orig_gpr3
      field, which is only used for system calls, and use it for the CFAR value
      for all exceptions/interrupts other than system calls.  This means we
      don't save the CFAR on system calls, which is not a great problem since
      system calls tend not to happen unexpectedly, and also avoids adding the
      overhead of reading the CFAR to the system call entry path.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      48404f2e
    • T
      powerpc: Add Initiate Coprocessor Store Word (icswx) support · 851d2e2f
      Tseng-Hui (Frank) Lin 提交于
      Icswx is a PowerPC instruction to send data to a co-processor. On Book-S
      processors the LPAR_ID and process ID (PID) of the owning process are
      registered in the window context of the co-processor at initialization
      time. When the icswx instruction is executed the L2 generates a cop-reg
      transaction on PowerBus. The transaction has no address and the
      processor does not perform an MMU access to authenticate the transaction.
      The co-processor compares the LPAR_ID and the PID included in the
      transaction and the LPAR_ID and PID held in the window context to
      determine if the process is authorized to generate the transaction.
      
      The OS needs to assign a 16-bit PID for the process. This cop-PID needs
      to be updated during context switch. The cop-PID needs to be destroyed
      when the context is destroyed.
      Signed-off-by: NSonny Rao <sonnyrao@linux.vnet.ibm.com>
      Signed-off-by: NTseng-Hui (Frank) Lin <thlin@linux.vnet.ibm.com>
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      851d2e2f
  4. 27 4月, 2011 1 次提交
  5. 20 4月, 2011 3 次提交
  6. 16 3月, 2011 1 次提交
  7. 15 3月, 2011 1 次提交
    • L
      powerpc/85xx: Workaroudn e500 CPU erratum A005 · ac6f1203
      Liu Yu 提交于
      This erratum can occur if a single-precision floating-point,
      double-precision floating-point or vector floating-point instruction on a
      mispredicted branch path signals one of the floating-point data interrupts
      which are enabled by the SPEFSCR (FINVE, FDBZE, FUNFE or FOVFE bits).  This
      interrupt must be recorded in a one-cycle window when the misprediction is
      resolved.  If this extremely rare event should occur, the result could be:
      
      The SPE Data Exception from the mispredicted path may be reported
      erroneously if a single-precision floating-point, double-precision
      floating-point or vector floating-point instruction is the second
      instruction on the correct branch path.
      
      According to errata description, some efp instructions which are not
      supposed to trigger SPE exceptions can trigger the exceptions in this case.
      However, as we haven't emulated these instructions here, a signal will
      send to userspace, and userspace application would exit.
      
      This patch re-issue the efp instruction that we haven't emulated,
      so that hardware can properly execute it again if this case happen.
      Signed-off-by: NLiu Yu <yu.liu@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      ac6f1203
  8. 04 3月, 2011 1 次提交
  9. 13 1月, 2011 1 次提交
  10. 24 8月, 2010 1 次提交
  11. 09 7月, 2010 1 次提交
  12. 05 5月, 2010 2 次提交
  13. 25 4月, 2010 1 次提交
  14. 01 3月, 2010 1 次提交
  15. 28 10月, 2009 1 次提交
  16. 20 8月, 2009 5 次提交
  17. 16 6月, 2009 1 次提交
    • B
      powerpc: Add memory clobber to mtspr() · 2fae0a52
      Benjamin Herrenschmidt 提交于
      Without this clobber, mtspr can be re-ordered by gcc vs. surrounding
      memory accesses. While this might be ok for some cases, it's not in
      others and I'm not confident that all callers get it right (In fact
      I'm sure some of them don't).
      
      So for now, let's make mtspr() itself contain a memory clobber until
      we can audit and fix everything, at which point we can remove it
      if we think it's worth doing so.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      2fae0a52
  18. 15 6月, 2009 1 次提交
    • P
      powerpc: Add compiler memory barrier to mtmsr macro · 4c75f84f
      Paul Mackerras 提交于
      On 32-bit non-Book E, local_irq_restore() turns into just mtmsr(),
      which doesn't currently have a compiler memory barrier.  This means
      that accesses to memory inside a local_irq_save/restore section,
      or a spin_lock_irqsave/spin_unlock_irqrestore section on UP, can
      be reordered by the compiler to occur outside that section.
      
      To fix this, this adds a compiler memory barrier to mtmsr for both
      32-bit and 64-bit.  Having a compiler memory barrier in mtmsr makes
      sense because it will almost always be changing something about the
      context in which memory accesses are done, so in general we don't want
      memory accesses getting moved from one side of an mtmsr to the other.
      
      With the barrier in mtmsr(), some of the explicit barriers in
      hw_irq.h are now redundant, so this removes them.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      4c75f84f
  19. 15 5月, 2009 1 次提交
    • P
      perf_counter: powerpc: supply more precise information on counter overflow events · 0bbd0d4b
      Paul Mackerras 提交于
      This uses values from the MMCRA, SIAR and SDAR registers on
      powerpc to supply more precise information for overflow events,
      including a data address when PERF_RECORD_ADDR is specified.
      
      Since POWER6 uses different bit positions in MMCRA from earlier
      processors, this converts the struct power_pmu limited_pmc5_6
      field, which only had 0/1 values, into a flags field and
      defines bit values for its previous use (PPMU_LIMITED_PMC5_6)
      and a new flag (PPMU_ALT_SIPR) to indicate that the processor
      uses the POWER6 bit positions rather than the earlier
      positions.  It also adds definitions in reg.h for the new and
      old positions of the bit that indicates that the SIAR and SDAR
      values come from the same instruction.
      
      For the data address, the SDAR value is supplied if we are not
      doing instruction sampling.  In that case there is no guarantee
      that the address given in the PERF_RECORD_ADDR subrecord will
      correspond to the instruction whose address is given in the
      PERF_RECORD_IP subrecord.
      
      If instruction sampling is enabled (e.g. because this counter
      is counting a marked instruction event), then we only supply
      the SDAR value for the PERF_RECORD_ADDR subrecord if it
      corresponds to the instruction whose address is in the
      PERF_RECORD_IP subrecord.  Otherwise we supply 0.
      
      [ Impact: support more PMU hardware features on PowerPC ]
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Acked-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      LKML-Reference: <18955.37028.48861.555309@drongo.ozlabs.ibm.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      0bbd0d4b
  20. 02 4月, 2009 1 次提交
  21. 11 3月, 2009 1 次提交
  22. 23 12月, 2008 1 次提交
  23. 04 8月, 2008 1 次提交
  24. 17 7月, 2008 1 次提交
  25. 01 7月, 2008 2 次提交
    • M
      powerpc: Add VSX context save/restore, ptrace and signal support · ce48b210
      Michael Neuling 提交于
      This patch extends the floating point save and restore code to use the
      VSX load/stores when VSX is available.  This will make FP context
      save/restore marginally slower on FP only code, when VSX is available,
      as it has to load/store 128bits rather than just 64bits.
      
      Mixing FP, VMX and VSX code will get constant architected state.
      
      The signals interface is extended to enable access to VSR 0-31
      doubleword 1 after discussions with tool chain maintainers.  Backward
      compatibility is maintained.
      
      The ptrace interface is also extended to allow access to VSR 0-31 full
      registers.
      Signed-off-by: NMichael Neuling <mikey@neuling.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      ce48b210
    • M
      powerpc: Introduce infrastructure for feature sections with alternatives · fac23fe4
      Michael Ellerman 提交于
      The current feature section logic only supports nop'ing out code, this means
      if you want to choose at runtime between instruction sequences, one or both
      cases will have to execute the nop'ed out contents of the other section, eg:
      
      BEGIN_FTR_SECTION
      	or	1,1,1
      END_FTR_SECTION_IFSET(FOO)
      BEGIN_FTR_SECTION
      	or	2,2,2
      END_FTR_SECTION_IFCLR(FOO)
      
      and the resulting code will be either,
      
      	or	1,1,1
      	nop
      
      or,
      	nop
      	or	2,2,2
      
      For small code segments this is fine, but for larger code blocks and in
      performance criticial code segments, it would be nice to avoid the nops.
      This commit starts to implement logic to allow the following:
      
      BEGIN_FTR_SECTION
      	or	1,1,1
      FTR_SECTION_ELSE
      	or	2,2,2
      ALT_FTR_SECTION_END_IFSET(FOO)
      
      and the resulting code will be:
      
      	or	1,1,1
      or,
      	or	2,2,2
      
      We achieve this by extending the existing FTR macros. The current feature
      section semantic just becomes a special case, ie. if the else case is empty
      we nop out the default case.
      
      The key limitation is that the size of the else case must be less than or
      equal to the size of the default case. If the else case is smaller the
      remainder of the section is nop'ed.
      
      We let the linker put the else case code in with the rest of the text,
      so that relative branches from the else case are more likley to link,
      this has the disadvantage that we can't free the unused else cases.
      
      This commit introduces the required macro and linker script changes, but
      does not enable the patching of the alternative sections.
      
      We also need to update two hand-made section entries in reg.h and timex.h
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fac23fe4
  26. 26 6月, 2008 1 次提交
  27. 03 3月, 2008 1 次提交
  28. 06 2月, 2008 1 次提交
  29. 25 1月, 2008 1 次提交
  30. 11 12月, 2007 1 次提交
  31. 17 9月, 2007 1 次提交