[1] Background :
    The GPMI does ECC read page operation with a DMA chain consist of three DMA
    Command Structures. The middle one of the chain is used to enable the BCH,
    and read out the NAND page.

    The WAIT4END(wait for command end) is a comunication signal between
    the GPMI and MXS-DMA.

[2] The current DMA code sets the WAIT4END bit at the last one, such as:

    +-----+               +-----+                      +-----+
    | cmd | ------------> | cmd | ------------------>  | cmd |
    +-----+               +-----+                      +-----+
                                                          ^
                                                          |
                                                          |
                                                     set WAIT4END here

    This chain works fine in the mx23/mx28.

[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
    be set not only at the last DMA Command Structure,
    but also at the middle one, such as:

    +-----+               +-----+                      +-----+
    | cmd | ------------> | cmd | ------------------>  | cmd |
    +-----+               +-----+                      +-----+
                             ^                            ^
                             |                            |
                             |                            |
                        set WAIT4END here too        set WAIT4END here

    If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
    In the next ECC write page operation, a DMA-timeout occurs.
    This has been catched in the MX6Q board.

[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
    and use the dma_ctrl_flags:
    ---------------------------------------------------------
      DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
      DMA_CTRL_ACK       : set the WAIT4END bit for this DMA Command Structure.
    ---------------------------------------------------------

[5] changes to the relative drivers:
    <1> For mxs-mmc driver, just use the new flags, do not change any logic.
    <2> For gpmi-nand driver, and use the new flags to set the DMA
        chain, especially for ecc read page.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Acked-by: NVinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Move the header to a more common place.
The mxs dma engine is not only used in mx23/mx28, but also used
in mx50/mx6q.  It will also be used in the future chips.

Rename it to mxs-dma.h, and create a new folder include/linux/fsl/ to
store the Freescale's header files.

change mxs-dma driver, mxs-mmc driver, gpmi-nand driver, mxs-saif driver
to the new header file.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Acked-by: NVinod Koul <vinod.koul@linux.intel.com>
Acked-by: NChris Ball <cjb@laptop.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The patch converts mxs-dma driver to clk_prepare/clk_unprepare by
using helper functions clk_prepare_enable/clk_disable_unprepare.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NVinod Koul <vinod.koul@linux.intel.com>

Before dma_transfer_direction was introduced to replace
dma_data_direction, some dmaengine device uses DMA_NONE of
dma_data_direction for some talk with its client drivers.
The mxs-dma and its clients mxs-mmc and gpmi-nand are such case.

This patch adds DMA_TRANS_NONE to dma_transfer_direction and
migrate the DMA_NONE use in mxs-dma to it.

It also fixes the compile warning below.

CC      drivers/dma/mxs-dma.o
drivers/dma/mxs-dma.c: In function ‘mxs_dma_prep_slave_sg’:
drivers/dma/mxs-dma.c:420:16: warning: comparison between ‘enum dma_transfer_direction’ and ‘enum dma_data_direction’
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

This is how the original Freescale code (unintentionally) worked,
because the code path which would have asserted the CLKGATE bit was
never actually reached in their code.
This fixes the nefarious "DMA timout" bug when multiple DMA channels
(e.g. GPMI NAND and MMC) are used at the same time.
If a better fix for this problem should be found, the clkgate handling
could be reinstated.
See http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/065228.html

Also reverse the order of mxs_dma_disable_chan() and
mxs_dma_reset_chan() in mxs_dma_control() because mxs_dma_reset_chan()
can only work when the DMA channel is enabled.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

Using a static variable for counting the number of CCWs attached to
a DMA channel when appending a new descriptor is not multi user safe.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

There is no need to have the clock enabled all the time the driver is
loaded.
It will be enabled anyway in mxs_dma_alloc_chan_resources() when a
channel is actually going to be used.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

fixup usage of dma direction by introducing dma_transfer_direction,
this patch moves dma/drivers/* to use new enum

Cc: Jassi Brar <jaswinder.singh@linaro.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Mika Westerberg <mika.westerberg@iki.fi>
Cc: H Hartley Sweeten <hartleys@visionengravers.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Zhang Wei <zw@zh-kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Yong Wang <yong.y.wang@intel.com>
Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
Cc: Boojin Kim <boojin.kim@samsung.com>
Cc: Barry Song <Baohua.Song@csr.com>
Acked-by: NMika Westerberg <mika.westerberg@iki.fi>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

After calling mxs_dma_disable_chan() for a channel, that channel
becomes unusable because some controller registers can only be written
when the clock is enabled via CLKGATE.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

We met some channels in abnormal state after disable.
Reset it to get a clean state.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

In general, the mxs-dma users get separate irq for each channel,
but gpmi is special one which has only one irq shared by all gpmi
channels.  It causes mxs_dma channel allocation function fail for
all other gpmi channels except the first one calling into the
function.

The patch gets request_irq call skipped for NO_IRQ case, and leaves
this gpmi specific quirk to gpmi driver to sort out.  It will fix
above problem if gpmi driver sets chan_irq as gpmi irq for only one
channel and NO_IRQ for all the rest channels.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This patch adds dma support for Freescale MXS-based SoC i.MX23/28,
including apbh-dma and apbx-dma.

* apbh-dma and apbx-dma are supported in the driver as two mxs-dma
  instances.

* apbh-dma is different between mx23 and mx28, hardware version
  register is used to differentiate.

* mxs-dma supports pio function besides data transfer.  The driver
  uses dma_data_direction DMA_NONE to identify the pio mode, and
  steals sgl and sg_len to get pio words and numbers from clients.

* mxs dmaengine has some very specific features, like sense function
  and the special NAND support (nand_lock, nand_wait4ready).  These
  are too specific to implemented in generic dmaengine driver.

* The driver refers to imx-sdma and only a single descriptor is
  statically assigned to each channel.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>