The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.

DT is also used by other projects than Linux kernel.  It is not a
good idea to rely on such an unofficial binding.

This commit
  - replaces "arm,amba-bus" with "simple-bus"
  - drops "arm,amba-bus" where it is used along with "simple-bus"
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Commit fa38a82096a1 ("scripts/dtc: Update to upstream version
53bf130b1cdd") added warnings on node name unit-address presence/absence
mismatch in device trees.

This patch fixes those warning on all the juno/vexpress platforms where
unit-address is present in node name while the reg/ranges property is
not present. It also adds unit-address to all smb bus node.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

This can be a example of adding SBSA Generic Watchdog device node
into some dts files for the Soc which contains SBSA Generic Watchdog.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NFu Wei <fu.wei@linaro.org>
[edited subject and moved change to dtsi file]
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Add Device Trees for Tronsmart Vega S95 Pro, Meta and Telos TV boxes.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Signed-off-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Signed-off-by: NAdam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

The qcom-spmi-mpp driver is now using string "digital" to denote
old "normal" functionality. Update DTS file.
Also update the powersource.
Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org>

Following the addition of the Alpine MSIX controller driver, add the
corresponding node in the Alpine v2 device tree.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NTsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds the initial support for the Alpine v2 EVP board from
Annapurna Labs (Amazon).
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NBarak Wasserstrom <barak@annapurnalabs.com>
Signed-off-by: NTsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The DT nodes representing the XOR engines were not placed at the
proper location to comply with the requirement of ordering DT nodes by
their unit address. This commit fixes this mistake.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Following the review from the DT maintainers, the DT binding for the
clocks has changed, and we now use a DFX server node exposing a
syscon, with the clock nodes being subnodes of the DFX server
node. This commit therefore updates the AP806 Device Tree file to use
this new DT binding.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.

The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:

 - An AP806 block that contains the CPU core and a few basic
   peripherals. The AP806 is available in dual core configurations
   (used in 7020 and 8020) and quad core configurations (used in 8020
   and 8040).

 - One or two CP110 blocks that contain all the high-speed interfaces
   (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
   and the 8K family chips have two CP110, giving them twice the
   number of HW interfaces.

In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:

 * armada-ap806.dtsi - definitions common to dual/quad ap806
   * armada-ap806-dual.dtsi - description of the two CPUs
     * armada-7020.dtsi - description of the 7020 SoC
     * armada-8020.dtsi - description of the 8020 SoC
   * armada-ap806-quad.dtsi - description of the four CPUs
     * armada-7040.dtsi - description of the 7040 SoC
       * armada-7040-db.dts - description of the 7040 board
     * armada-8040.dtsi - description of the 8040 SoC

The CP110 blocks are not described yet, and will be part of future
patch series.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Add DT node to enable SLIMpro Mailbox I2C Driver for
X-Gene v2 platforms.
Signed-off-by: NDuc Dang <dhdang@apm.com>

Add mailbox device tree node for APM X-Gene v2 platform.
Signed-off-by: NDuc Dang <dhdang@apm.com>

Add DT node to enable SLIMpro Mailbox I2C Driver for
X-Gene v1 platforms.
Signed-off-by: NDuc Dang <dhdang@apm.com>

Mailbox device tree node for APM X-Gene platform.
Signed-off-by: NFeng Kan <fkan@apm.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

This patch updates gpio-keys node that supports power-off for
X-Gene v2 Merlin board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: NQuan Nguyen <qnguyen@apm.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>

xgene-gpio-sb driver now supports configuring some GPIO pins
as interrupt pins. This patch adds the required fields for GPIO
standby controller DT node of X-Gene v2 platform to work with
this new driver change.
Signed-off-by: NQuan Nguyen <qnguyen@apm.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>

This patch updates gpio-keys node that supports power-off for
X-Gene v1 Mustang board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: NDuc Dang <dhdang@apm.com>

We should set SW15 to pin 2-3 side on the board before we use CN9
as USB host or peripheral.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This board has a MAX3355 chip. However, we cannot use the extcon/max3355
driver because the ID pin doesn't connect to a gpio pin (in other words,
it connects to the SoC specific pin).
And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now.
So, this patch enables usb2_phy of channel 1 and 2.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Use recently added fallback compatibility string in r8a7795 device tree.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support.
Signed-off-by: NAi Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NAi Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: squashed some fixes and added mmc-caps]
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch updates the digital voltage levels from corner values to
microvolts as we are going to use s1 regulator directly for vddcx
instead of s1_corner.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch enables the lpass on DB410C. LPASS is used as cpu dai for
both analog and digital audio.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds lpass node to the SOC.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds pinctrls required for digital and analog audio via lpass.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds manual pull up setting for usb otg indicating that the
vbus is vbus is not routed to USB controller/phy therefore enables
pull-up explicitly before starting controller.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

Update APM X-Gene standby GPIO controller DTS entries to enable it
as interrupt controller.

[dhdang: update patch subject]
Signed-off-by: NY Vo <yvo@apm.com>
Signed-off-by: NQuan Nguyen <qnguyen@apm.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NDuc Dang <dhdang@apm.com>

Update Merlin DT PCP PLL clock node to reflect compatible
string change to reflect v2 hardware.

[dhdang: change patch subject]
Signed-off-by: NLoc Ho <lho@apm.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>

This patch adds poweroff button device node to support
poweroff feature on hip05 d02 board.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

Instead of using the generic armv8-pmuv3 compatibility, use
the more specific Cortex A57 compatibility.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

Extract clocks and put it specific file to help with platform
autogeneration.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>