Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There are 43 includes of asm/mach-types.h by files that don't
reference anything from that file.  Remove these unnecessary
includes.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Inflate requires some dynamic memory allocation very early in the boot
process and this is provided with a set of four functions:
malloc/free/gzip_mark/gzip_release.

The old inflate code used a mark/release strategy rather than implement
free.  This new version instead keeps a count on the number of outstanding
allocations and when it hits zero, it resets the malloc arena.

This allows removing all the mark and release implementations and unifying
all the malloc/free implementations.

The architecture-dependent code must define two addresses:
 - free_mem_ptr, the address of the beginning of the area in which
   allocations should be made
 - free_mem_end_ptr, the address of the end of the area in which
   allocations should be made. If set to 0, then no check is made on
   the number of allocations, it just grows as much as needed

The architecture-dependent code can also provide an arch_decomp_wdog()
function call.  This function will be called several times during the
decompression process, and allow to notify the watchdog that the system is
still running.  If an architecture provides such a call, then it must
define ARCH_HAS_DECOMP_WDOG so that the generic inflate code calls
arch_decomp_wdog().

Work initially done by Matt Mackall, updated to a recent version of the
kernel and improved by me.

[akpm@linux-foundation.org: coding-style fixes]
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Mikael Starvik <mikael.starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Tweak the Feroceon match/mask in arch/arm/boot/compressed/head.S to
match a couple of newer Feroceon cores (such as the 88fr571vd with
CPU ID 0x56155710, and the 88fr131 with CPU ID 0x56251310) as well.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Core ftrace support for the ARM architecture, which includes support
for dynamic function tracing.
Signed-off-by: NAbhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Signed-off-by: NEric Miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

U-Boot puts an image at the load address specified in the uImage
header before jumping to the entry point.

In the CONFIG_ZBOOT_ROM case ZBOOT_ROM_TEXT is the right load
address.
Signed-off-by: NUwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The cache replacement policy on the Feroceon core doesn't guarantee
that reading through a linear chunk of memory flushes the entire cache.
This is however what the default method for ARMv5TE cores does.

Although the Feroceon is an ARMv5TE core, it implements the same
cache handling instructions as the ARMv5TEJ cores, and must use it for
proper cache flush.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The default ARMv4 method consisting of reading through some memory
area isn't compatible with the cache replacement policy of some
ARMv5TEJ compatible cache implementations.  It is also a bit wasteful
when a dedicated instruction can do the needed work optimally.

It is hard to tell if all ARMv5TEJ cores will support the used CP15
instruction, but at least all those implementations Linux currently
knows about (ARM926 and ARM1026) do support it.

Tested on an OMAP1610 H2 target.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Tested-by: NGeorge G. Davis <gdavis@mvista.com>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>

AT91RM9200 needlessly verifies machine-type numbers of
supported / known platforms and overwrites it for unknown
ones. Remove it.
Signed-off-by: NGuennadi Liakhovetski <lg@denx.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

According to ARM7TDMI Technical Reference Manual (ARM DDI 0210C) writing
to the DCC data write register coproc dest registers are 1 and 0, not 0
and 1.

ARM920T TRM (ARM DDI 0151C) agrees on that.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: NUwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The variable CFLAGS is a wellknown variable and the usage by
kbuild may result in unexpected behaviour.
On top of that several people over time has asked for a way to
pass in additional flags to gcc.

This patch replace use of CFLAGS with KBUILD_CFLAGS all over the
tree and enabling one to use:
make CFLAGS=...
to specify additional gcc commandline options.

One usecase is when trying to find gcc bugs but other
use cases has been requested too.

Patch was tested on following architectures:
alpha, arm, i386, x86_64, mips, sparc, sparc64, ia64, m68k

Test was simple to do a defconfig build, apply the patch and check
that nothing got rebuild.
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>

since both u-boot and blob support passing MACH_TYPE_LUBBOCK to the
kernel, it should be quite safe to remove this
Signed-off-by: Neric miao <eric.y.miao@gmail.com>
Acked-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rename CONFIG_S3C2410_LOWLEVEL_UART_PORT to be
CONFIG_S3C_LOWLEVEL_UART_PORT as we move to using
plat-s3c for base of S3C operations.
Signed-off-by: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The 'i' and 'zi' targets short-circuit the dependencies for
'install' and 'zinstall' targets; these are useful for
installing the kernel on platforms which have make but no
compiler installed.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This is to avoid a compiler warning for overriding the built-in "putc"
function.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The current arch/arm/boot/compressed/head.S code only supports cores
to ARMv6 with the old CPU Id format. This patch adds support for the
new ARMv6 with the new CPU Id and ARMv7 cores that no longer have the
ARMv4 cache operations.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

font_acorn_8x8.o was being built in drivers/video/console/ twice
during a build _in the same location_ - once for the kernel proper,
and once for the decompressor.  The result is when you came to run an
install target, the kernel was always rebuilt due to this file
apparantly having been built with different compiler arguments.

Solve this by making a local copy at build time in the decompressor's
directory.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

If MACH_GTWX5715 is set in Kconfig, this code sets the mach id
automatically. Howeber, this means that any IXP4xx kernel which
is setup to support the gtwx5715 board will not successfully boot
on any other board.

If the bootloader sets the wrong mach id, it should be set correctly
by a kernel shim.
Signed-off-by: NMichael-Luke Jones <mlj28@cam.ac.uk>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NNicolas Pitre <npitre@mvista.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In the arch/arm/boot/compressed/head.S file, the contents of the
literal pool accumulated during the relocatable code must be dumped
before reloc_end.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

ARMv7 support code requires a valid stack for saving/restoring
registers as the whole D-cache flushing function is more complex. This
patch ensures that the SP register is not corrupted.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

inflate_fixed and huft_build together use around 2.7k of stack.  When
using 4k stacks, I saw stack overflows from interrupts arriving while
unpacking the root initrd:

do_IRQ: stack overflow: 384
 [<c0106b64>] show_trace_log_lvl+0x1a/0x30
 [<c01075e6>] show_trace+0x12/0x14
 [<c010763f>] dump_stack+0x16/0x18
 [<c0107ca4>] do_IRQ+0x6d/0xd9
 [<c010202b>] xen_evtchn_do_upcall+0x6e/0xa2
 [<c0106781>] xen_hypervisor_callback+0x25/0x2c
 [<c010116c>] xen_restore_fl+0x27/0x29
 [<c0330f63>] _spin_unlock_irqrestore+0x4a/0x50
 [<c0117aab>] change_page_attr+0x577/0x584
 [<c0117b45>] kernel_map_pages+0x8d/0xb4
 [<c016a314>] cache_alloc_refill+0x53f/0x632
 [<c016a6c2>] __kmalloc+0xc1/0x10d
 [<c0463d34>] malloc+0x10/0x12
 [<c04641c1>] huft_build+0x2a7/0x5fa
 [<c04645a5>] inflate_fixed+0x91/0x136
 [<c04657e2>] unpack_to_rootfs+0x5f2/0x8c1
 [<c0465acf>] populate_rootfs+0x1e/0xe4

(This was under Xen, but there's no reason it couldn't happen on bare
  hardware.)

This patch mallocs the local variables, thereby reducing the stack
usage to sane levels.

Also, up the heap size for the kernel decompressor to deal with the
extra allocation.
Signed-off-by: NJeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Cc: Tim Yamin <plasmaroo@gentoo.org>
Cc: Andi Kleen <ak@suse.de>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Ian Molton <spyro@f2s.com>

Add the picotux 200 ARM board:
 - Enable its machine type in the filter in head.S
 - Add configuration option
 - Add board initialisation
 - Add default configuration
Signed-off-by: NSimon Richter <Simon.Richter@kleinhenz.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Many files include the filename at the beginning, serveral used a wrong one.
Signed-off-by: NUwe Zeisberger <Uwe_Zeisberger@digi.com>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>

We currently have a hardcoded 4 megabyte uncompressed kernel image
size limit, which is easily exceeded by, for example, enabling some of
the various kernel debugging options.

When setting up the initial page tables (which is where this 4M limit
is hardcoded), it's actually relatively easy to find out the true size
of the uncompressed kernel image and create enough page table entries
for things to fit, so this patch makes it so.

In the decompressor, we also need to know the size of the uncompressed
kernel image, to figure out whether there is any chance that uncompressing
the kernel might overwrite the compressed kernel image stored elsewhere
in memory. We don't have that info at this boot stage, though, so we
approximate the size of the uncompressed kernel by taking the compressed
kernel image size and allowing for a maximum 4x expansion.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.
Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Adds support for CONFIG_DEBUG_ICEDCC for ARM11.
Tested on ARM1136 (OMAP2420).
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The iop33x loadsp hunk in arch/arm/boot/compressed/head.S serves
no purpose -- remove it.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rename CONFIG_ARCH_IOP321 to CONFIG_ARCH_IOP32X and
CONFIG_ARCH_IOP331 to CONFIG_ARCH_IOP33X.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Nicolas Pitre

According to the Intel PXA27x Processor Family Specification
Update document (doc.nr. 280071-009) erratum E7, some care must be taken
to locate the disabling and re-enabling of the MMU to the beginning of a
cache line to avoid problems in some circumstances.

Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this
up.
Signed-off-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NJörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>

Patch from Lennert Buytenhek

This patch adds support for the Ajeco 1ARM Single Board Computer, a
VME form factor SBC based on the Atmel AT91 SoC, with 64M RAM, seven
serial ports, three ethernet ports, IDE, CF, USB host and device,
and S-Video/VGA out.--
Signed-off-by: NLennert Buytenhek &lt;buytenh@wantstofly.org&gt;Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

As for RETINSTR, LOADREGS is a left-over from the 26-bit days.
Remove it.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Andrew Victor

This patch adds support for an additional 4 AT91RM9200-based boards:

1. Conitec ARM&EVA  [MACH_CARMEVA]
   (http://www.conitec.net/english/linuxboard.htm)

2. KwikByte KB920x  [MACH_KB9200]
   (http://kwikbyte.com/KB9202_description_new.htm)

3. Embest ATEB9200  [MACH_ATEB9200]
   (http://www.embedinfo.com/english/product/ATEB9200.asp)

4. Sperry-Sun KAFA board  [MACH_KAFA]
   (unknown)
Signed-off-by: NAndrew Victor <andrew@sanpeople.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Catalin Marinas

This code was still using the old format for the ARMv6 CPU id and it wasn't
flushing the caches on the MPCore CPU (and other ARM1176 cores). The patch
changes the mask bits to cope with the new id format.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Uwe Zeisberger

 a) use coprocessor 14
 b) make reading the dcc status volatile
Signed-off-by: NUwe Zeisberger <Uwe_Zeisberger@digi.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>